Vectorizing Quantum Control: A RISC-V Vector Extension Architecture for Scalable Qubit Systems

Abstract: The Quantum Control Processor (QCP) bridges the gap between compiler toolchains and control electronics, and is responsible for translating compiled quantum circuits into executable instructions that directly manipulate qubits and handle measurement feedback. However, existing designs rely primarily on customized instruction sets, limiting design reuse and requiring significant effort to build supporting toolchains. Furthermore, efficiently addressing qubits and scheduling operations in highly scalable scenarios remains a critical challenge. In this work, we present a vectorized quantum control approach built upon the RISC-V Vector (RVV) engine with a quantum-oriented extension. Leveraging the high parallelism of RVV, our approach can address up to 128 qubits in a single instruction. We also embed parameterized rotation information into the instruction set, enabling dynamic tuning of gate rotations in hybrid quantum-classical programs. To support mid-circuit measurements, we design a hardware-based halt-resume protocol that resumes pipeline execution within 80 $ns$ of receiving the measurement result. Comprehensive evaluation using both RISC-V toolchains and FPGA prototypes demonstrates that our design achieves up to 2.52$\times$ speedup over the baseline in program execution time, with excellent scalability.

• The paper presents a scalable vectorized quantum control processor leveraging RISC-V extensions to enable parallel operations on up to 128 qubits per instruction.
• It introduces quantum-specific ISA extensions that compress quantum instructions, achieving up to 2.52× speedup and efficient mixed-precision handling.
• The design integrates hardware-managed measurement synchronization with sub-100 ns latency, ensuring real-time adaptive quantum feedback.

Vectorized Quantum Control with HiSEP-Q 2.0: RISC-V Vector Extension Architecture for Scalable Qubit Systems

Introduction

Quantum Control Processors (QCPs) serve a critical role as the bridging hardware layer between compiler toolchains and quantum control electronics. The scalability of such classical control infrastructures increasingly emerges as a limiting bottleneck when targeting quantum systems beyond tens or hundreds of qubits, especially in the Noisy Intermediate-Scale Quantum (NISQ) and fault-tolerant quantum computing (FTQC) regimes. Traditional QCPs rely on bespoke or highly customized ISAs, complicating toolchain integration and hindering hardware-software co-design flexibility.

HiSEP-Q 2.0 proposes a vectorized quantum control architecture based on the RISC-V Vector (RVV) extension, integrating qubit addressability and quantum gate operation parallelism directly into a widely adopted, scalable ISA substrate. The design leverages vectorized SIMD semantics to control up to 128 qubits per instruction and embeds quantum rotation parameters for hybrid quantum-classical workflows. This architectural approach significantly increases code density, realization of parallel gate operations, and overall classical-to-quantum instruction throughput.

Figure 1: HiSEP-Q~2.0 in the quantum software stack; the dashed boundary identifies components introduced in this work.

Architecture and ISA Extensions

The HiSEP-Q 2.0 architecture consists of three principal components: the quantum-extended RVV ISA, the QVCP (Quantum Vector Control Processor) implementation, and a QASM-to-binary compiler targeting the full hardware stack. The ISA extends the standard RVV (OP-V major opcode) to incorporate quantum instructions with operational classes for single-qubit, two-qubit, global, and variable parameterized rotations. These new instructions leverage RVV's length-agnostic model, exploiting the LMUL grouping mechanism for scalable simultaneous qubit operation.

Qubit indices are encoded as 8-bit elements within vector registers, enabling a single vector instruction to address up to 128 qubits per operation, configurable at runtime through vsetvli. Specialized instructions such as QV.ROT.V permit mixed-precision operand handling, supporting high-precision angle parameters per 8-bit qubit index without auxiliary control instructions. The per-instruction 5-bit immediate (Blk_imm) provides fine-grained gate timing metadata for hardware-level temporal scheduling.

Figure 2: Overall architecture of the Ibex-coupled quantum vector engine and its execution back end, enabling hybrid classical/quantum workflows.

Microarchitectural Realization

The QVCP implements the extended ISA on top of an Ibex RV32IMC scalar host and a Vicuna-based vector coprocessor. Two execution domains—scalar and quantum vector—are tightly coupled via a host/coprocessor interface (QXIF), preserving standard RISC-V software semantics and enabling efficient offloading of quantum instructions to the vector engine.

Quantum instructions are decoded, dispatched, and executed within the QVCP core. Their semantic payload is exported via a dedicated quantum sideband path to the QVCP backend, which includes the Synchronizer and Quantum Adapter modules. The Synchronizer manages pipeline stalls and halts for measurement (MCM) support, while the Quantum Adapter transforms quantum event streams into precise, per-qubit, time-scheduled firing pulses.

Figure 3: Main blocks of QVCP Core, including the dedicated quantum sideband export mechanism.

A notable feature is hardware-level management of measurement synchronization. The halt-resume protocol enables pipelined execution to pause precisely at measurement operations and resume with sub-100 ns latency after external measurement results are received, guaranteeing deterministic and efficient mid-circuit measurement (MCM) handling essential for adaptive, feedback-driven quantum algorithms.

Evaluation and Numerical Results

The full hardware stack is realized in RTL (Verilog/SystemVerilog), deployed on a Xilinx ZCU216 RFSoC FPGA. HiSEP-Q 2.0 supports a complete OpenQASM 3.0 to binary toolchain, facilitating dense vectorized encoding from high-level quantum circuits down to hardware-executable binaries. Benchmarks employ representative circuits from MQT Bench, spanning a variety of quantum algorithmic workloads.

HiSEP-Q 2.0 demonstrates a geometric mean speedup of 1.26× over HiSEP-Q 1.0, reaching up to 2.52× in execution time for circuits with high parallel gate structure. Speedups are most pronounced in workloads characterized by layers of independent two-qubit gates, where the new vector instructions effectively collapse batched gate invocations into a single operation. Workloads with deep data dependencies exhibit more modest gains due to inherent serialization constraints.

Figure 4: Execution time speedup compared to HiSEP-Q~1.0, especially for highly parallel workloads.

Latency and throughput measurements confirm that quantum event streams are pipelined with near single-cycle event issuance per qubit in the steady state. The halt-resume MCM protocol achieves execution resumption within 80 ns, a latency well within coherence times of leading physical qubit platforms.

Figure 5: Instruction latency across different quantum gate types and vector configurations.

Resource utilization for configurations up to 128 qubits demonstrates near-linear scaling of the quantum dispatcher (approximately 90 LUTs and 263 FFs per qubit), with the scalar/vector front-end remaining invariant. The entire architecture consumes less than 4% of the FPGA's available resources in the 32-qubit configuration, validating practical integration potential for large-scale quantum-classical systems.

Figure 6: Resource scalability (LUT, FF) of HiSEP-Q 2.0 versus qubit count $N$, showing linear scaling in the quantum dispatcher.

Practical and Theoretical Implications

By inheriting the RISC-V ecosystem, HiSEP-Q 2.0 eliminates the need for bespoke compilation and verification frameworks, aligning quantum-classical hardware co-design with broader open-source and industry-standard methodologies. The vectorized gate encoding directly addresses scalability and code density bottlenecks that are acute in FTQC and QEC contexts. The robust, ISA-level abstraction for both qubit addressability and hybrid parameter delivery provides a solid foundation for future quantum software/hardware codesign.

HiSEP-Q 2.0's microarchitectural approach to measurement synchronization and mixed-precision operand handling highlights a path toward latency-efficient, feedback-driven control of quantum hardware—critical for emerging quantum error correction codes and real-time adaptive quantum algorithms. The demonstrated scalability further suggests that full-stack, large-$N$ QCP architectures built on open standards are viable without architectural re-designs.

Future directions include architectural optimizations targeting deeper pipeline integration, tighter coupling with cryogenic control electronics, and extension of the vectorization paradigm for even larger quantum processor scales, and adaptation for post-NISQ and FTQC circuits with heterogeneous timing and qubit connectivity constraints.

Conclusion

HiSEP-Q 2.0 establishes a scalable, toolchain-compatible vector quantum control architecture, leveraging the RVV extension to RISC-V for dense parallelism in quantum circuit execution. Strong numerical results—peak 2.52× speedup, hardware-managed MCM within 80 ns, and linear resource scaling—validate the approach for near-term and future quantum computing systems. The quantum-vector overlay outlined by HiSEP-Q 2.0 offers a blueprint for next-generation QCPs addressing the code density, latency, and hardware-software integration demands of scalable quantum-classical platforms.