Comparing and learning figures of merit for quantum circuit compilation

Abstract: To make quantum algorithms executable on a particular quantum device, they need to be compiled into circuits that respect constraints of the quantum hardware. This compilation usually involves multiple steps, where many hardware-compatible circuits are generated, and the best circuit is selected. To say which circuit is best, the quality of a circuit is generally quantified by a $\textit{figure of merit}$ (FoM). For FoMs, there is a trade-off between ease of calculation and accuracy in predicted execution quality. Commonly used FoMs, e.g., the number of gates, circuit depth, etc., are easy to evaluate, but do not directly capture the effects of circuit structure and noise. On the other end of the spectrum are FoMs that require full circuit execution and take a prohibitively long time to evaluate. One example is the probability of successful trials (PST), i.e., the probability of obtaining the initial state after running the quantum circuit followed by its inverse. Here, we investigate advantages and disadvantages of different FoMs, and formulate the properties of an ideal FoM. Based on our results, we propose wPST, a weighted version of the PST that accounts for individual qubits, not just the whole state. To quickly predict PST and wPST, we design machine learning models that take into account both the quantum circuit and quantum hardware data. In numerical simulations and experiments on quantum processors, we find that our machine learning-predicted FoMs outperform commonly used FoMs, increasing the correlation with the true PST or wPST by over 50%. To make our model useful for quantum compilers, we devise a two-step process to predict the wPST for non-transpiled quantum circuits: first, we predict the additional quantum gates required for the given quantum circuit, and then we predict the wPST, accounting for coherence times in the quantum device.

• The paper introduces the weighted PST metric and ML predictors that more accurately assess quantum circuit quality compared to traditional metrics.
• It details a two-step prediction pipeline using circuit-derived and hardware-aware features, achieving a 50% improved correlation with ground-truth fidelity.
• The study establishes a new Pareto-optimal trade-off between computational efficiency and precision, validating ML-based figures of merit for practical compiler integration.

Comparing and Learning Figures of Merit for Quantum Circuit Compilation

Introduction

The work, "Comparing and learning figures of merit for quantum circuit compilation" (2607.03275), critically analyzes the landscape of figures of merit (FoMs) for quantum circuit compilation—the quantitative metrics used to assess how well a compiled circuit performs on real quantum hardware. It addresses the challenge of identifying FoMs that are both computationally efficient and highly correlated with actual circuit execution quality, rather than resorting to shallow proxies like gate counts or circuit depth. The study introduces a weighted probability of successful trials (wPST) metric, demonstrates machine learning models to predict this and other FoMs with high accuracy, and outlines a practical two-step prediction pipeline for use in quantum compilers.

Limitations of Traditional Figures of Merit

Classical FoMs—such as total gate count, two-qubit gate count, and circuit depth—are rapidly computable and have dominated both compiler design and experimental evaluation. However, as shown in extensive empirical evaluation, these metrics are only weakly correlated with actual computation fidelity, especially for hardware with nonuniform connectivity, gate error rates, and decoherence profiles.

The study explores the limitations of "distance-based" FoMs (e.g., Hellinger distance, TVD) computed directly from comparison of noisy and ideal output distributions. For large quantum circuits, these metrics become exponentially expensive and are often unreliable, particularly for broad output distributions where noise correlation to fidelity is lost.

To illustrate the dependence of all common FoMs on noise and output correlation, the paper examines experimental and simulated cases. For instance, in four-qubit circuits subjected to increasing noise, both fidelity and PST decay rapidly, while distance-based metrics only strongly correlate in the single-output regime but fail as distributions broaden.

Figure 1: Measurement-based FoMs and their variation with noise for two four-qubit circuits.

PST and the Case for Weighted PST

The probability of successful trials (PST) metric measures, in essence, the probability of returning to the all-zero state after running a compiled circuit followed by its inverse (i.e., the Loschmidt echo). This metric captures the aggregate effect of errors and noise on the entire circuit, with established strong correlation to device fidelity. However, PST is binary with respect to errors—a single bit flip collapses the metric to zero, masking the gradation of noise impact across the qubits.

To address this, the weighted PST (wPST) metric is proposed, wherein the contribution of each post-execution measurement outcome is weighted by the proportion of bits matching the reference (usually all-zero) state, with an acceptance threshold. This granularity allows wPST to distinguish between single- and multi-qubit errors, directly mapping partial circuit success.

Figure 2: Values of fidelity, PST, distance-based metrics, and wPST for a quantum circuit with increasing number of bit-flip errors.

Machine Learning-Based FoM Prediction

Direct computation of PST and wPST is experimentally expensive and infeasible for integration in inner compiler optimization loops. The core contribution of the paper is the construction of machine learning predictors for PST/wPST, incorporating both circuit structural features and hardware-specific data (e.g., connectivity, coherence times, per-qubit error rates).

The overall pipeline involves:

• Extraction of a high-information feature vector from the circuit DAG, including qubit count, gate count, two-qubit gate count, depth, entanglement ratio, program communication, parallelism, critical depth, and liveliness.
• Incorporation of device-specific information such as per-qubit $T_1$/$T_2$ times and coupling map degrees, mapped onto the feature vector using custom-engineered hardware-aware features.

Figure 3: Workflow of the machine learning-based FoM prediction pipeline, integrating circuit and hardware features for XGBoost model training and inference.

Figure 4: Directed acyclic graph (DAG, right) representation of a four-qubit quantum circuit (left).

The best-performing models were based on ensemble decision-tree architectures (XGBoost), tuned for both rapid training and inference and low prediction error.

Quantitative Performance and Feature Importance

The ML predictors were validated on both simulated and real data from multiple IBM quantum processors (Strasbourg, Torino, Miami, Brussels). Across all cases, PST/wPST predicted by the ML models achieved 50% higher correlation with ground-truth values (as judged by Pearson coefficients) compared to traditional circuit-derived FoMs—0.92 to 0.97 averages for ML PST/wPST, vs. ≤0.40 for simple circuit metrics. Importantly, this held across both random circuits and highly structured MQT benchmarks.

Figure 5: Root mean square error (RMSE) between the true and predicted PST and wPST for random circuits across qubits for the 12-qubit quantum simulator.

Figure 6: Importance of different features across different quantum devices in the (a) PST and (b) wPST prediction models.

Feature importance analysis reveals that program communication and two-qubit gate counts dominate, with additional contributions from entanglement ratio and depth. This is consistent across devices but shows notable shifts depending on hardware architecture.

Two-Step Prediction for Non-Transpiled Circuits

To integrate the wPST predictor into compiler pipelines—where circuits under consideration have not yet been mapped to hardware—the paper presents a two-step ML prediction architecture:

1. Feature Vector Estimation: Predicts the features (notably, extra two-qubit gates and program communication) that would result from mapping the ideal circuit to the target hardware, using only coupling map and hardware info.
2. Final wPST Prediction: Uses the augmented feature vector and device coherence data to output the final wPST estimate.

Both steps are implemented via efficient ML regressors and maintain low RMSEs, even when extrapolating to unseen circuits and hardware layouts.

Figure 7: RMSE in prediction of (a) the number of two-qubit gates and (b) program communication for a 12-qubit system on a simulator, validating the accuracy of the feature prediction step.

Figure 8: Root mean squared error for predicted wPST using direct and two-step schemes in the IBM Torino device.

Computational Complexity and the Pareto Frontier

The study situates its wPST ML-predicted metric as a new Pareto-optimal point in the trade-off between FoM computational cost and correlation with execution fidelity. Traditional metrics are fast but weak. Simulation- or measurement-based metrics (e.g., Hellinger distance, fidelity) are accurate but scale exponentially with qubit count. The ML wPST approach achieves high accuracy (near the best physical metrics) at polynomial time cost, practical for integration into compiler optimization loops.

Figure 9: Trade-off between model accuracy and computational complexity for different FoMs; the wPST ML model is close to the Pareto frontier.

Practical and Theoretical Implications

The practical implication is clear: quantum compilation pipelines can now integrate an FoM that is hardware-aware, discriminates fine-grained error rates, and is efficiently computable, producing better-compiled circuits for NISQ-class hardware with inhomogeneous noise and topology. This enables larger, more reliable quantum computations within existing device constraints.

Theoretically, wPST's capacity to interpolate between binary and analog error accumulation opens new avenues for error mitigation benchmarking and adaptive noise-aware compilation strategies. The ML methodology outlined for FoM regression generalizes to more complex hardware models, potentially accommodating new error sources or architectural constraints.

Future Prospects

Open questions remain, particularly regarding the effect of PST/wPST's dependence on circuit inversion (doubling depth in evaluation circuits) and its reflection of noise resilience in original circuits. Further progress will likely involve:

• End-to-end integration and benchmarking of ML FoM predictors within mainstream quantum compilers,
• Exploration of alternative feature representations (e.g., richer graph neural embeddings),
• Extension of the two-step prediction pipeline to compilation strategies with mid-circuit measurements, dynamical decoupling, or adaptive optimization,
• Systematic extension of the Pareto frontier with new FoMs and estimation strategies for both NISQ and future fault-tolerant devices.

Conclusion

This study provides a comprehensive empirical and methodological foundation for hardware-aware, machine-learned figures of merit for quantum circuit compilation. The proposed wPST, combined with efficient ML predictors, represents a significant advance in closing the gap between theoretical metric design and practical, scalable compiler evaluation for near-term quantum computing platforms. This approach informs both the theory of circuit quality metrics and the engineering of compilation workflows, substantially improving the correlation between FoM and real device performance without incurring the prohibitive costs of full-circuit simulation or repeated hardware execution.