Learning to rank quantum circuits for hardware-optimized performance enhancement

Abstract: We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit ibmq_guadalupe device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a $1.8\times$ reduction in selection error when compared to the baseline approach and a $3.2\times$ reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.

• The paper introduces a machine learning approach that ranks quantum circuit layouts using a phenomenological error model to optimize hardware performance.
• It leverages real hardware data to achieve a 1.8× to 3.2× reduction in selection error compared to conventional methods.
• The method improves circuit fidelity by systematically addressing hardware constraints and contextual noise characteristics.

Learning to Rank Quantum Circuits for Optimized Hardware Performance

Introduction to the Layout Selection Problem

Quantum computing has made significant strides, with a variety of quantum processors now accessible via commercial, academic, and public-sector platforms. These advancements pose a crucial challenge: selecting the optimal architecture and qubit technology for executing a given quantum algorithm. This challenge accentuates the necessity for robust techniques to predict the performance of quantum circuits on different hardware accurately.

The process of mapping abstract qubits in a quantum circuit to physical qubits on a device, known as layout selection, is pivotal for maximizing circuit fidelity. Layout selection emerges as a considerable challenge due to hardware constraints, such as limited qubit connectivity and native gate sets. With the fidelity of quantum circuits being highly sensitive to the chosen layout, there is an urgent need for strategies that can systematically assess and select the most effective layout for execution on quantum hardware.

The Emergence of Machine Learning-Based Ranking for Circuit Layout Selection

In the quest to address the layout selection problem, a novel machine-learning-based method has been proposed to rank logically equivalent quantum circuits based on their performance. The method introduces a "circuit score" used for ranking, which is parameterized by a phenomenological error model. This model accounts for various error mechanisms inherent to quantum computing hardware, such as gate errors and decoherence times.

By fitting the parameters of this model through a training procedure employing data from actual hardware performance, the approach offers a nuanced way to anticipate the efficacy of different quantum circuit layouts. This method stands apart by considering the contextual nature of device noise and error, enabling more accurate performance predictions without the exhaustive need for quantum tomography.

Comparative Analysis and Key Results

The presented approach was rigorously tested on IBM quantum hardware, showcasing significant advancements over existing methods. The method consistently outperformed both random layout selection and another known method, Mapomatic, in predicting layouts that yield lower noise and higher fidelity. Specifically, the new method achieved a 1.8× and 3.2× reduction in selection error compared to Mapomatic and random selection, respectively.

These results underscore the potential of integrating machine learning with phenomenological modeling to enhance quantum circuit performance predictively. By effectively ranking the possible layouts of quantum circuits, this approach aids in navigating the complex landscape of hardware-specific limitations and noise characteristics.

Implications and Future Directions

This research contributes a predictive tool to the field of Quantum Characterization, Validation, and Verification (QCVV), serving both theoretical and practical advancements in quantum computing. It highlights the complexity of accurately predicting quantum circuit performance solely based on hardware specifications and underscores the importance of context-aware solutions.

The findings beckon a broader application of machine learning in quantum computing, especially in automating and optimizing quantum circuit design and deployment. Future research could expand this ranking framework to accommodate a wider array of quantum algorithms and hardware architectures, further bridging the gap between quantum computing's theoretical potential and practical execution.

Conclusion

The development of a machine-learning-based method for quantum circuit layout selection marks a significant step toward realizing optimized quantum computing performances. By leveraging data-driven insights and sophisticated modeling, this approach paves the way for more intelligent, efficient, and adaptable quantum computing platforms. As the quantum computing landscape continues to evolve, such innovations will be crucial in harnessing the full power of quantum technologies.