LogicIR: Logic Gate Networks for Image Restoration

Abstract: Image restoration aims to reconstruct high-quality images from degraded low-quality inputs. As the computational demands of image restoration models continue to rise, there is growing interest in lightweight architectures optimized for fast and efficient inference. Logic gate networks (LGNs), which operate using fundamental logic operations such as NAND and XOR, have recently emerged as a promising direction for achieving highly efficient computation. However, their potential remains largely untapped in the domain of image restoration. In this work, we introduce LogicIR, the first LGN specifically designed for image restoration tasks. LogicIR incorporates a UNet-inspired architecture composed entirely of logic gates. In addition, we propose a differentiable bit decoding layer and an index shuffling mechanism that improves information propagation across logic gates. Experimental results across multiple image restoration benchmarks demonstrate that LogicIR achieves strong performance with significantly reduced computational cost, establishing LogicIR as a viable and efficient alternative for image restoration. The source code is available at https://github.com/jimmy9704/LogicIR

• The paper introduces a fully binarized UNet-style logic-gate network using NAND/XOR operations, differentiable bit decoding, index shuffling, MSB loss, and straight-through fine-tuning for image restoration.
• LogicIR-S achieves 27.40 dB PSNR on BSD68 denoising with 41.4 G BOPs, while the four-rotation variant reaches 27.71 dB and surpasses BBCU-lite using 6.5× fewer operations.
• The method runs 20.3× faster than BBCU-lite on GPU, reduces estimated energy from 0.69 to 0.03 mJ, and supports efficient FPGA or ASIC deployment, though super-resolution and ensemble overhead remain open challenges.

LogicIR extends logic gate networks (LGNs) to image restoration, a domain previously dominated by full-precision CNNs, binarized neural networks (BNNs), and look-up table (LUT) methods. The central contribution is an architecture that performs inference exclusively through discrete binary logic operations—NAND, XOR, and their peers—with no trainable weights or floating-point arithmetic, while retaining the hierarchical feature modeling that restoration tasks demand (2606.26609).

Motivation and positioning

Existing efficient restoration approaches each carry structural drawbacks. BNN-based methods such as BBCU, Bi-Real, and ReActNet replace multiplications with binary operations but retain full-precision adders in residual blocks and non-binarized input/output layers, which complicates deployment on FPGAs and ASICs. LUT-based methods such as SR-LUT, MuLUT, and HKLUT suffer from exponential growth of table size with receptive field, capping spatial context. LGNs sidestep both issues: inference uses only logic gates, and differentiable relaxation over gate selections enables gradient-based training (2606.26609). However, prior convolutional LGNs (CLGNs) were built for classification and lack three ingredients essential for restoration: a bit decoding mechanism to map binary activations back to pixel values, hierarchical representations, and a locality inductive bias compatible with randomly connected logic nodes.

Architecture

The paper first establishes a baseline, StackedCLGN, which serially stacks convolutional logic layers with 8-bit-plane inputs and outputs. Its failure is stark: 17.19 dB PSNR on BSD68 ($\sigma=25$) versus 27.62 dB for BBCU-lite, demonstrating that naive stacking of logic layers is insufficient. LogicIR addresses this with a UNet-style encoder–decoder of convolutional logic layers (fixed tree depth $d=3$), where blocks combine $1\times1$ and $3\times3$ logic convolutions. Residual additions are replaced by encoder–decoder skip connections via channel-wise concatenation; max pooling and transposed convolutions are replaced by pixel unshuffle/shuffle; and the network predicts a residual image added to the degraded input.

Two components are novel. The differentiable bit decoding layer converts a multi-channel binary output into a normalized residual via a bitcount operation, mapping activations $\mathbf{A}\in\{0,1\}^{C\times H\times W}$ to $\bar{\mathbf{R}}\in[-1,1]^{H\times W}$, with a learnable scalar $\alpha$ expanding the effective output range. This avoids direct bit-plane regression, where less significant planes are noisy and semantically inconsistent. Index shuffling, inspired by ShuffleNet, cyclically reorders the channel groups feeding each logic tree kernel, breaking the group isolation of CLGN's grouped connections that otherwise form independent sub-networks.

Training combines an L2 reconstruction loss with an auxiliary MSB loss computed against a reference reconstructed from only the top four bit planes, weighted by $\lambda$. A straight-through estimator (STE) fine-tuning stage follows main training to close the gap between soft gate selection during training and hard discrete selection at inference. A rotational ensemble (2 or 4 rotations) compensates for the limited pattern diversity induced by random connectivity.

Results

The efficiency claims are substantial. On BSD68 denoising at $\sigma=25$:

Method	BOPs	PSNR
DnCNN-lite (FP)	36.6 T	28.24
BBCU-lite (BNN)	1097.2 G	27.62
HKLUT (LUT)	499.4 G	27.34
StackedCLGN	39.7 G	17.19
LogicIR-S	41.4 G	27.40
LogicIR-S-4RT	169.3 G	27.71

LogicIR-S matches ReActNet using 2.8% of its BOPs and outperforms HKLUT with 15.7% of its BOPs; LogicIR-S-4RT surpasses BBCU-lite with 6.5× fewer operations. Notably, LogicIR is fully binarized end-to-end, whereas competing BNNs keep first/last layers in full precision—their fully binarized variants (e.g., BBCU-lite-fully at 25.23 dB) degrade sharply, so the comparison is not merely against weakened baselines. Similar patterns hold for JPEG deblocking (28.62 dB on LIVE1 with 36.7% of HKLUT's operations) and deraining (22.95 dB on Test100, exceeding all BNN baselines with under 21% of their operations).

Hardware measurements reinforce the operation counts: on GPU, LogicIR-S runs in 28.2 ms versus 571.6 ms for BBCU-lite (20.3× faster); estimated energy is 0.03 mJ versus 0.69 mJ, and TSMC N5 chip area is 0.09 mm² versus 2.44 mm². FPGA implementations on an Intel Cyclone V confirm scalability across channel widths $C$ from 64 to 256, providing a straightforward resource knob.

Ablations attribute gains incrementally: bit decoding alone lifts StackedCLGN from 17.19 to 26.83 dB, the UNet backbone adds 0.32 dB, index shuffling adds 0.43 dB, and MSB loss plus STE fine-tuning bring LogicIR-S to 27.83 dB. Index shuffling is shown to prevent the saturation that fixed grouping exhibits as logic layers deepen. For color images, per-channel RGB processing with shared weights retains most of joint-RGB quality at roughly half the BOPs and is adopted as the default.

Limitations

The paper restricts evaluation to resolution-preserving tasks. Super-resolution, which requires explicit upsampling, poses architectural challenges within a pure logic-gate framework—designing scalable upsampling mechanisms there remains open. Additionally, the rotational ensemble multiplies inference cost (up to 4× BOPs), and the STE fine-tuning stage is needed precisely because soft-to-hard gate selection introduces a train/inference mismatch that the method mitigates rather than eliminates.

Conclusion

LogicIR demonstrates that image restoration can be performed entirely through discrete logic operations at competitive quality, achieving state-of-the-art efficiency among lightweight methods across denoising, deblocking, and deraining. Its combination of a UNet-style logic architecture, differentiable bit decoding, and index shuffling establishes a workable template for logic-based low-level vision, with hardware results supporting practical edge deployment.