Routing Codes: High-Rate Quantum LDPC Codes with Short, Parallel Non-Local Connectivity

Abstract: Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are comparable to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism fundamentally eliminates wiring crossings in superconducting multi-layer architectures and drastically simplifies the scheduling of atom movement in neutral-atom arrays. Under circuit-level simulation, the weight-7 routing codes reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.

• The paper presents routing codes, a new qLDPC family that reduces hardware overhead by engineering short, parallel non-local connectivity while preserving high encoding rates.
• The methodology leverages toroidal lattice constructions and symmetric routing sequences to ensure stabilizer commutativity and efficient, parallel syndrome extraction.
• Simulations demonstrate that routing codes require about 8× fewer physical qubits than surface codes while achieving competitive error thresholds (~0.5%) and lower hardware complexity.

High-Rate Quantum LDPC Codes with Parallel Non-Local Connectivity: Routing Codes

Introduction

This work introduces "routing codes," a new family of quantum low-density parity-check (qLDPC) codes specifically designed to ameliorate the hardware overheads associated with implementing high-rate quantum error correction on superconducting and neutral-atom quantum architectures. While qLDPC codes theoretically promise improved encoding rates compared to the surface code, their realization is obstructed by the need for extensive non-local connectivity, which is challenging for practical layouts. Routing codes address these challenges by engineering short, parallel non-local couplings and low qubit degree, while preserving high encoding rates, thus enabling feasible, hardware-centric deployments of qLDPC codes (2606.25330).

Background and Motivation

Fault-tolerant quantum computing requires encoding logical qubits with sufficient redundancy to withstand errors induced by decoherence and operational noise. The surface code remains the dominant choice for QEC due to its high threshold and planar architecture supporting only nearest-neighbor interactions. However, its asymptotically vanishing encoding rate imposes prohibitively large resource overheads, impeding scalability. qLDPC codes overcome the rate limitation but demand qubit interactions spanning longer distances with increased qubit connectivity.

Yet, idealized all-to-all connectivities are unattainable in realistic superconducting or atomic platforms due to constraints including physical wiring, frequency crowding, and atom transport errors. State-of-the-art BB codes, for example, offer improved rates but still involve crossing long-range couplings that generate severe layout complexity. Thus, a gap persists between theoretical qLDPC optimality and practical realizability. Routing codes are constructed to directly bridge this divide.

Construction of Routing Codes

Routing codes are defined on a toroidal lattice, leveraging systematic sequences of "routing vectors" dictating the paths by which syndrome qubits interact with data qubits via iSWAP (CXSWAP) gates. Unlike prior work, routing codes generalize beyond only nearest-neighbor connectivity, but crucially restrict all non-local couplings within each code instance to a single direction and ensure parallel, non-crossing geometry. The construction applies symmetry constraints—specifically, identical and time-reversed symmetric routing sequences for X and Z checks—which automatically ensure stabilizer commutativity.

The algebraic formulation employs group ring polynomials to represent stabilizers. The full code family is parameterized by the routing vector sequence, torus size, and partitioning into data and syndrome qubits. All syndrome extraction circuits are parallelizable, enabling efficient syndrome measurement cycles with minimal gate depth. The codes are quantum CSS codes, with distance computation reduced to an integer program over the support of stabilizer generators.

Performance and Hardware Metrics

Error Correction Performance

Circuit-level simulations demonstrate that weight-7 routing codes—where each stabilizer generator acts on 7 qubits—achieve encoding rates closely matching BB codes, with thresholds competitive with canonical surface code values (~0.5%). Notably, for a fixed logical error rate, routing codes require approximately 8$\times$ fewer physical qubits than surface code implementations. For example, at $p=10^{-3}$, [[100, 8, 10]] routing code outperforms rotated surface codes in qubit efficiency.

Upper bounds on circuit-level distance, obtained via randomized BP-OSD decoding, universally exceed those of BB codes at equal theoretical distance, indicating robust performance scaling at lower error rates.

Hardware Layout Complexity

Routing codes provide manifest hardware advantages for both leading implementation technologies:

• Superconducting Qubits: The maximal qubit degree is 4 or 5, rather than 6 or higher in BB codes; all non-local couplings are parallel, obviating wiring crossings. When evaluated using the Hardware-Aware Layout (HAL) framework, routing codes exhibit a reduced number of routing tiers (3–4 vs. 5–6 for BB codes), shortened coupler lengths, and lower requirements for bump bonds and through-silicon vias. The composite hardware complexity metric $C_{hw}$ remains $<$2 for all routing code instances examined, compared to $>2$ for BB codes.
• Neutral-Atom Arrays: The maximal shuttle distance for non-local couplings is reduced by a factor of 3 (e.g., vectors of (2,1) vs. (6,3)), directly decreasing transport time, motional heating, and atom loss probability. Moreover, the parallel geometry allows highly efficient and conflict-free scheduling of shuttle operations, reducing the minimal number of timestep layers required for interactive gates.

Practical Implications

Routing codes constitute a scalable solution for near-term quantum error correction due to their explicit reconciliation of code-theoretic and hardware-engineering considerations. As high-fidelity, non-local gates and multi-tier interconnects become standard in superconducting circuits, and large-scale atom transport is routine in neutral-atom arrays, routing codes are directly implementable. By eliminating wiring crossings and minimizing non-local interaction distance, these codes reduce device complexity, lower error rates, and enable more viable logical qubit densities, accelerating the timeline for meaningful, large-scale quantum computing.

These improvements are robust to decoder choices; simulation results are decoder-agnostic, but further gains can be expected with task-adapted neural or improved BP decoders.

Future Directions

Several open directions arise:

• Extending construction to twisted tori and non-translation-invariant topologies to further reduce overhead and enable planarization.
• Allowing multiple non-local vectors and optimizing routing vector sequences for even lower resource consumption.
• Adapting routing code constructions to irregular or defective hardware, facilitating fault-tolerant QEC on non-ideal chips.
• Generalizing hardware-adaptive routing for chip heterogeneity and defective region avoidance.
• Developing complete protocols for performing logical gate operations (e.g., lattice surgery) natively within the routing code paradigm remains a key open problem.

Conclusion

Routing codes represent a significant step in reconciling the high-rate, low-overhead promise of qLDPC codes with the stringent physical constraints of contemporary hardware. Through parallel, short, non-local connectivity and explicit circuit constructions, they set a new benchmark for actionable quantum error correction codes. Their flexibility and hardware-alignment position them as a leading candidate for QEC in the next era of scalable quantum architectures (2606.25330).