General circuit mapping algorithm for neutral atom quantum computers

Abstract: Neutral atom quantum computers (NAQC) are emerging as a promising, scalable quantum computing platform because of their long qubit coherence, flexible qubit arrangement, and multiqubit gate capabilities. However, circuit execution often requires physically moving qubits, making compilation a critical optimization challenge. We propose a circuit independent mathematical framework built on graph-theoretic combinatorial optimization that determines the minimal number of required qubit transfers. This model captures spatial constraints specific to NAQC platforms with zone-limited gate operations and multi-qubit gates. From this framework, we encode the qubit mapping problem as a nonlinear integer program and solve it using a genetic algorithm, enabling trade-offs between minimizing the total traveled distance and the number of parallel transfer operations. Compared to the state-of-the-art scalable compiler for zoned architectures, our approach consistently finds fewer transfers. Depending on the optimization focus, our method produces shorter traveled distances or fewer parallel transfer operations. This work provides both theoretical guaranties and a practical tool for efficient, architecture-aware quantum circuit compilation. As a result, practitioners can generate hardware-aware mappings that reduce movement-induced errors and better exploit atom transfer parallelism, directly improving execution efficiency on NAQC devices.

• The paper introduces a graph-theoretic genetic algorithm for mapping circuits in neutral atom quantum computers that minimizes qubit transfers.
• It employs a nonlinear integer formulation with stick encoding to efficiently optimize both travel distance and parallel transfer operations.
• Empirical benchmarks show that the method outperforms or matches state-of-the-art compilers like ZAC and MQT in reducing mapping-induced errors.

General Circuit Mapping Algorithm for Neutral Atom Quantum Computers

Overview

This work, "General circuit mapping algorithm for neutral atom quantum computers" (2606.20503), proposes a novel, mathematically rigorous, and architecture-aware compilation algorithm tailored for neutral atom quantum computing (NAQC) platforms. The authors present a graph-theoretic combinatorial optimization framework that systematically minimizes physical qubit movement—an essential cost in NAQC—while explicitly handling the specific spatial and operational constraints of both monolithic and zoned hardware architectures. The proposed method encodes the circuit mapping problem as a nonlinear integer program, solved using a genetic algorithm (GA) to explore trade-offs between minimizing the total traveled distance and the number of parallel transfer operations (PTOs). Numerical results demonstrate that this approach achieves or surpasses state-of-the-art compilers such as ZAC and MQT in both transfer minimization and PTO optimization.

Neutral Atom Platform Constraints and Motivation

NAQC hardware utilizes arrays of optically trapped ultracold atoms, typically implemented as 2D (or 3D) grids with precise, programmable atomic positions. Gate execution—especially for entangling Rydberg gates—requires physically moving atoms to specific interaction regions, thus imparting a significant compilation challenge: optimizing the sequence and parallelism of atomic transfers is critical due to transfer-induced errors and limited atom lifetimes.

Figure 1: Schematic overview of the proposed mapping algorithm, detailing platform constraints, quantum circuit decomposition, graph construction, and the genetic optimization workflow.

Unlike superconducting or ion-trap platforms, NAQC architectures often leverage separated spatial zones for computation, termed monolithic (M-arch) or zoned (Z-arch) arrangements. In Z-arch, the physical partitioning of the entanglement and storage zones mandates additional movements and careful mapping. Multi-qubit gate capabilities (e.g., CCZ gates) further complicate the mapping process. Past works have introduced various heuristic or simulated annealing-based mappers, but lacked explicit lower bounds and generally applicable formulations.

Graph-Theoretic Formulation

The mapping algorithm critically relies on converting each quantum circuit to a directed acyclic multi-stage graph, where vertices represent gate instructions (possibly involving multiple qubits per instruction per stage) and edges encode static versus dynamic (transfer) qubit assignments between stages.

Figure 2: Transformation of a quantum circuit into a digraph, with distinct matchings representing alternative transfer configurations across stages.

Figure 3: Encapsulation of scheduled circuit portions into subgraphs according to spatial zones (Z-arch), enabling local and inter-zone transfer analysis.

For every stage transition, the associated bipartite subgraph (matching problem) is solved to maximize static qubit allocations (minimize transfers). By leveraging maximum-weighted matchings, the global minimum transfer count for the circuit is obtained by a stage-wise sum of local optima. The formulation is shown to extend from M-arch to arbitrary multi-zone arrangements, supporting a wide gate set including multi-qubit gates.

Efficient Encoding and Genetic Optimization

The solution space for mapping problem after enforcing minimal transfer constraints still possesses nontrivial combinatorial degrees of freedom (DoFs), especially regarding the concrete (x,y) grid positions of atomic sticks and substicks (chain of qubit assignments per instruction per zone and stage), and the orderings of qubit groups within complex instructions.

Figure 4: 3D stick encoding of circuit mapping, with atomic positions in the 2D grid (XY) over time (stage axis), and colored lines representing qubit stick assignments.

Figure 5: Illustration of stick substicks, forks, and tines; internal permutations represent the accessible DoFs exploited during GA-based optimization.

The authors introduce a stick/substick encoding, which captures both spatial placement and combinatorial reordering within instructions, reducing the optimization dimensionality. The mapping optimization is performed via a genetic algorithm (no crossover), with solutions evolved by random local moves and encoding-internal shuffling, scored according to either total distance, PTO count, or hybrid metrics reflecting hardware preferences.

Parallel Transfer Operations and Routing

Atom transport is further complicated by hardware motion rules (e.g., AOD constraints, collision avoidance), which restrict permissible sets of transfers that can be executed in parallel (defining PTOs). The algorithm constructs a transfer digraph $G_T$ for each transition, identifies cycles requiring additional "helper" moves to break, and applies a greedy assignment of compatible transfer sets to PTOs respecting axis (Manhattan/Euclidean) movement constraints.

Figure 6: Cycle detection and breaking in transfers; minimal transfer addition ensures physically realizable sequences without atomic collisions.

Figure 7: Realistic atom routing in the grid, with reserved space ensuring collision-free travel for moved atoms.

Figure 8: PTO construction example, showing color-coded parallel transfer sets and their executable order.

Empirical Evaluation and Results

Benchmarks on canonical and algorithmic circuits (e.g., QFT, WState, SWAP-test) establish that this approach consistently meets or closely approximates the theoretical minimal transfer limit established by the global matching procedure, outperforming state-of-the-art alternatives such as ZAC and MQT.

Figure 9: Comparative benchmark on total transfer count, PTO count, and total distance for ten circuits; the orange line (this method) tracks closely to the transfer lower bound (green).

The genetic optimization’s flexibility is underscored by demonstrating trade-offs: optimizing PTO count can produce fewer parallel operation steps than MQT/ZAC, while optimizing for distance yields the shortest aggregate travel at some cost to parallelism.

Figure 10: Effects of different GA scoring functions (min PTO, min distance) on benchmark results; altering the optimization objective drives circuit-specific trade-offs.

Practical and Theoretical Implications

The presented framework provides an explicit, architecture-aware, theoretically sound baseline for NAQC mapping, applicable across a variety of hardware topologies and circuit gate sets. The explicit control over optimization metrics enables practitioners to adapt mapping strategies quantitatively to their hardware’s error and speed budgets, whether minimizing exposure to motion-related errors (distance) or wall-clock latency (PTOs). The stick encoding method further streamlines large-scale instance handling and provides tight integration with realistic atomic movement scheduling.

Future Directions

This mapping paradigm readily generalizes to forthcoming NAQC systems with more specialized zones (e.g., multi-qubit gates occupying separate spatial regions) and potentially heterogeneous atom arrangements. Extension to dynamic reconfiguration, explicit integration of hardware error/fidelity models into the mapping cost function, and hybridization with other combinatorial optimization or reinforcement learning solvers are plausible developments. The interface between quantum circuit scheduling and mapping (stage formation) remains another area for algorithmic innovation, especially as NAQC system scales increase.

Conclusion

This work introduces a comprehensive, mathematically grounded, and empirically validated algorithm for NAQC circuit mapping that is both flexible and optimal with respect to transfer minimization, PTO sequencing, and hardware-aware cost trade-offs. By formulating the problem in terms of graph matchings and leveraging efficient encodings plus GA-based meta-optimization, the method enables improved execution efficiency and reduced mapping-induced infidelity on current and advanced NAQC platforms (2606.20503).