PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation

Abstract: Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work, we propose PANDA, an LLM-enhanced framework that bridges high-level design intent to final layout by actively managing cross-stage dependencies through guided topology synthesis, substructure-aware sizing, and constraint-driven layout generation. This shifts automation from algorithm-centric execution to intent-centric co-design, reducing turnaround time from days or weeks to hours while improving design performance.

• The paper introduces a unified LLM-driven framework that integrates topology synthesis, analog sizing, placement, and routing for effective performance closure.
• It employs hierarchical Bayesian optimization and constraint-driven placement to ensure semantic-to-physical traceability and rapid design evaluations.
• Experimental results demonstrate a significant turnaround time reduction from days to hours, achieving robust post-layout electrical performance.

PANDA: LLM-Enhanced, Performance-Driven Intent-to-Layout Analog Design Automation

Motivation and Context

Despite extensive analog CAD research, end-to-end AMS design automation remains impractical largely due to persistent stage decoupling: (1) high-level design intent is not systematically translated into executable topologies, (2) circuit sizing is performed without physical awareness, and (3) placement/routing flows receive only partial or out-of-date constraints, decoupled from schematic requirements. Moreover, traditional algorithm-centric flows are not easily adaptable to post-layout feedback, which is essential for performance closure. This fragmentation creates manual bottlenecks, rapid error amplification, and design cycles that extend from days to weeks.

PANDA introduces an agentic paradigm for analog circuit design by leveraging an LLM as the central coordinator. The framework connects design intent to layout generation in a unified pipeline, with structured handoffs at each stage to preserve cross-dependencies (Figure 1).

Figure 1: Comparison between traditional automated analog design flow and the agentic flow in PANDA.

Methodology

PANDA is composed of four tightly coupled design stages: topology synthesis, analog sizing, constraint-driven placement, and detailed routing. Each stage is orchestrated by an LLM, which translates intent and intermediate artifacts into actionable, stage-specific constraints, utilizing reusable Skills and explicit execution handoffs. This design ensures semantic-to-physical traceability, solver stability, and reproducibility across the flow (Figure 2).

Figure 2: Overview of PANDA methodology.

Topology Synthesis

PANDA integrates an LLM-guided SPICE subcircuit synthesizer (AnalogXpert [analogxpert]), which interprets design intent and constraints into explicit schematic structures. The agent narrows the combinatorial search via an extensible subcircuit library and iterative structural repairs, synthesizing functionally valid, interface-consistent topologies as machine-readable artifacts for downstream tasks.

Substructure-Aware Analog Sizing

Given the fixed topology, PANDA uses a multi-stage hierarchical Bayesian optimization engine (MOSTAR [fan_mostar_2025]) to map design constraints into transistor-level parameters. MOSTAR efficiently traverses high-dimensional objectives by exploiting subcircuit graph representations (L2G-GNNs), additive Gaussian processes, and symmetry-aware acquisition. The resulting sizing.json explicitly encodes device attributes and parasitic constraints for physical implementation.

Constraint-Driven Placement

Placement is executed within a constraint-optimization framework that converts schematic- and sizing-level information into geometric, area, and symmetry constraints. Placement objects are clustered, symmetry pairs and grouping constraints are derived, and incremental legalization resolves physical implementability. Artifacts are emitted in pl.json to ensure reproducible handoff to the router.

Routing and Layout Synchronization

PANDA aggregates all previous outputs to generate detailed routing directives, leveraging SAGERoute/SAGERoute2.0 for analog- and mixed-signal-specific constraint handling. Pin interfaces, geometries, and LVS consistency are directly synchronized to the template, with iterative PEX closure for post-layout performance feedback. The looped execution enables the LLM to select and refine candidates, closing the gap between pre-layout and post-layout performance.

Execution Flow and Experimentation

PANDA’s flow is observable, traceable, and largely machine-executable, as every stage emits standardized JSON artifacts and is driven by explicit, structured Skills. Execution is transparent, with trial-level records and prompt-level intermediates available for post-hoc analysis.

Design evaluation focuses both on efficiency—turnaround time reduction from days to several hours for full layout closure—and post-layout performance preservation. For a three-stage OTA, post-layout gain (76.11 dB, PM = $65.3^\circ$) aligns with design intent, even as UGB drops post-parasitic inclusion, confirming coherent constraint propagation and realistic post-layout correction. For a StrongARM comparator, post-layout results show practical power/delay overheads but no performance failure (Figure 3).

Figure 3: Generated layout result for the OTA case.

Strong Claims and Quantitative Outcomes

• Turnaround time is consistently reduced from multi-day manual flows to several hours due to the closed-loop, agentic execution paradigm.
• Cross-stage consistency is structurally enforced and auditable: No artifact is transferred via ambiguous text but strictly through machine-readable, structured data.
• Post-layout electrical closure is machine-driven: Parasitic-aware simulation feedback is directly looped to the LLM, enabling practical design closure without manual intervention.
• LLM acts as a skillful agent rather than a token generator, decomposing flows into reusable, prompt-executed Skills, thereby enhancing reliability and auditability.

Theoretical Implications and Future Directions

PANDA demonstrates that LLMs are not merely speculative planners but can be embedded as deterministic flow coordinators, leveraging explicit handoffs to domain-specific tools (simulators, optimizers, placers, routers). This agentic approach collapses traditional barriers between design intent and layout execution while providing a blueprint for robust, auditable analog CAD systems. The structured handoff paradigm also facilitates composition with future learning-based or MACRO frameworks, including joint learning for placement and routing, constraint synthesis, and in-context skill selection [heChatEDALargeLanguage2024, chen24artisan, laiAnalogCoderAnalogCircuit2024, yinADOLLMAnalogDesign2024].

Further research should focus on:

• Improving self-reflective capabilities within LLM agents (expanded self-feedback, skill selection, and evaluation) [madaan2023selfrefineiterativerefinementselffeedback, renze2024selfreflectionllmagentseffects].
• Integrating more effective post-layout performance predictors, including GNN-based parasitic estimators [liu_parasitic-aware_2021, xu_performance-driven_nodate].
• Enhancing planning interfaces for broader analog/mixed-signal block support and service modularity.

Conclusion

PANDA, as an LLM-driven, intent-to-layout analog design automation system, demonstrates that holistic stage coupling, agentic coordination, and structured machine execution collectively overcome traditional automation bottlenecks. The flow achieves substantial reductions in design cycle time, preserves schematic-physical consistency, and robustly closes the layout-performance loop—defining a scalable path for future analog design frameworks.

---

References

• "PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation" (2606.15052)
• AnalogXpert [analogxpert]
• MOSTAR [fan_mostar_2025]
• He et al., "ChatEDA: A LLM Powered Autonomous Agent for EDA" [heChatEDALargeLanguage2024]
• Chen et al., "Artisan: Automated Operational Amplifier Design via Domain-specific LLM" [chen24artisan]
• Lai et al., "AnalogCoder: Analog Circuit Design via Training-Free Code Generation" [laiAnalogCoderAnalogCircuit2024]
• Yin et al., "ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of LLMs" [yinADOLLMAnalogDesign2024]
• Madaan et al., "Self-Refine: Iterative Refinement with Self-Feedback" [madaan2023selfrefineiterativerefinementselffeedback]
• Renze et al., "Self-Reflection in LLM Agents: Effects on Problem-Solving Performance" [renze2024selfreflectionllmagentseffects]
• Liu et al., "Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization" [liu_parasitic-aware_2021]
• Xu et al., "Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation" [xu_performance-driven_nodate]