Uncertainty-Aware End-to-End Co-Design of Neural Network Processors: From Training and Mapping to Fabrication

Abstract: Designing a neural network processor is an end-to-end co-design problem: network architecture and training budget determine the inference workload; hardware mapping decisions determine chip area, latency, and energy; and these characteristics govern fabrication yield and manufacturing cost. In practice, these decisions are made in separate stages, and existing co-design methodologies are tightly coupled to specific algorithms, making it difficult to improve one component without reworking the entire pipeline. This paper presents a unified framework, grounded in monotone co-design theory, that composes four interoperable design blocks spanning network training, chip mapping, wafer-level fabrication, and compute resource allocation. Each block exposes only a functionality-resource interface to the rest of the system, so any block can be refined without structural changes elsewhere. A central contribution is the treatment of uncertainty: rather than collapsing stochastic outcomes into point estimates, the framework introduces Confidence, the inverse of success probability, as an explicit and optimizable resource alongside cost, time, and power. Three case studies validate the approach. The first recovers Pareto-optimal implementations across heterogeneous application scenarios. The second confirms that Confidence functions as a continuously tunable design knob rather than a post-hoc diagnostic. The third demonstrates that improving a single block's implementation set automatically propagates to the global Pareto front, without modifying the co-design diagram.

• The paper introduces an end-to-end co-design framework that unifies neural network training, hardware mapping, fabrication, and computation to manage uncertainty as a design resource.
• The methodology leverages monotone co-design theory and surrogate modeling to decouple subsystem complexities and enable modular, principled trade-offs.
• The paper demonstrates that explicit confidence management leads to optimized resource allocation and improved performance over traditional sequential design approaches.

Uncertainty-Aware End-to-End Co-Design for Neural Network Processors

Introduction and Motivation

Designing neural network processors (NNPs) constitutes a fundamentally end-to-end co-design problem encompassing neural network architecture, training budget, hardware mapping, chip fabrication, and allocation of computational resources. This paper proposes a unified, compositional framework based on monotone co-design theory, enabling principled integration across abstraction levels—from neural network selection and training, through hardware mapping and wafer-level fabrication, to compute resource allocation. The methodology systematically exposes only the functionality–resource interface of each subsystem to the global co-design pipeline, thereby decoupling internal algorithmic choices and supporting modular improvements.

A pivotal innovation is the explicit inclusion of Confidence (inverse success probability) as a tunable resource, promoting uncertainty quantification as a first-class citizen in hardware–software co-design alongside cost, time, and power. Unlike prior approaches, which collapse stochastic outcomes into deterministic proxies or post-hoc diagnostics, this framework supports continuous trade-offs between reliability and resource expenditure.

Theoretical Foundations

The foundation of this work leverages monotone co-design theory as delineated in [censi2015mathematical], which provides an order-theoretic formalism for modular system composition. Each design block is modeled as a monotone design problem with implementation (MDPI), encapsulating its set of possible implementations, functionality–resource relations, and internal stochasticity. The interfaces between blocks are strictly defined in terms of functionalities delivered and resources consumed, ensuring compositionality and permitting block-wise improvements without affecting the global co-design diagram.

The framework extends to distributional uncertainty following [huangDistributionalUncertaintyAdaptive2026], allowing for explicit probabilistic modeling of stochasticity arising from training, mapping heuristics, and process variation in fabrication. Confidence is formalized as an optimizable resource, mapped to the inverse of the joint probability of satisfying all imposed constraints.

Figure 1: Software-to-fabrication co-design diagram outlining data flow and resource interfaces between network, mapping, fabrication, and computation blocks.

Modeling and Surrogates for Stochastic Co-Design Blocks

Network Training

The network selection and training pipeline is parameterized over network architectures, training settings, and computational budgets. Training outcomes are modeled via a stochastic process, with a Gaussian surrogate (mean–variance parameterization) used for deployment. The accuracy trajectory is represented as a hybrid curve interpolating early exponential improvement and late-stage power-law convergence. This surrogate is calibrated using HW-NAS-Bench data, with the residuals demonstrating near-constant variance in the regime of accuracy change—justifying the homoscedastic model structure.

Figure 2: Fitted learning-curve surrogate for the network training pipeline, showing mean and percentile accuracy trajectories.

Chip Mapping and Hardware Design

Hardware mapping employs a genetic algorithm (GA)-based solver, exploring a discrete, high-dimensional space defined by network embedding configuration, hardware constraints, and dataflow decisions. The mapping solution yields chip-level metrics (latency, energy, area), modeled using a three-component mixture distribution which captures near-optimal, moderate-quality, and poor mappings. Surrogate fitting leverages independent GA runs and regression across solver epochs, with parameter identification optimized via RMSE minimization.

Figure 3: Chip mapping workflow: the GA evolves hardware mappings encoded by genomes, culminating in evaluation of area, energy, and latency metrics.

A nearest-neighbor approach indexes empirical LEA tuples from profiling data, preserving the coupling of physical metrics and supporting realistic multi-objective optimization.

Figure 4: Nearest-neighbor lookup in $(t, [\mathtt{x}]_o)$ space, constraining candidate mappings by budget and metric thresholds.

Validation using Wasserstein distance illustrates monotonic convergence of the surrogate to empirical distributions and accurate confidence estimation for early-stage solver budgets.

Figure 5: Wasserstein-1 distance between the fitted mixture and empirical LEA distributions, confirming progressive surrogate accuracy.

Fabrication Modeling

Fabrication is modeled using a negative binomial yield distribution parameterized by defect density and clustering. Stochastic outcomes are propagated via Monte Carlo sampling, delivering distributions over the number of yielded chips as a function of chip area, monetary budget, and process node.

Figure 6: Fabrication MDPI block, representing the mapping from area/cost to yielded chips under process variation.

Figure 7: Composed cost vs. yield distribution for a selected process node, illustrating increasing variance at large production volumes.

Computation Distribution Planning

The computational workload is distributed between CPU and GPU hardware, calibrated with normalized throughput and wall-clock time. The co-design framework models calibration maps and hardware alternatives as MDPIs, supporting allocation of resource budgets between the training and mapping blocks. Hardware catalogs are indexed for performance normalization, supporting cost-driven or power-driven planning.

Figure 8: Computation Distribution Planner block, showing decomposition of workloads and resource normalization across hardware alternatives.

Case Studies and Numerical Results

Pareto-Optimal End-to-End Co-Design

The complete framework is instantiated in multiple application scenarios, ranging from baseline cost-driven designs (e.g., cleaning robots) to highly constrained implants (multi-dimensional area, energy, latency, accuracy, and chip yield constraints). Pareto fronts spanning power–cost and time–confidence demonstrate distinct regimes of resource expenditure and constraint satisfaction.

Figure 9: Pareto front for power–cost under baseline and constrained scenarios, showing shifting boundaries with tightening constraints.

Strong numerical results validate that the composed framework jointly recovers implementation choices—network architecture, hardware mapping, fabrication node, and compute hardware—that would not emerge from sequential optimization.

Confidence as a Design Resource

The framework reveals confidence as a tunable knob rather than a diagnostic; increasing reliability (high confidence) requires disproportionate resource investment. The time–confidence Pareto front quantifies the premium of high-reliability operation absent in deterministic approaches.

Figure 10: Time–Confidence Pareto front showing sharp resource transitions between low and high reliability regimes.

Surrogate Validation and Algorithmic Decoupling

Empirical distributions for all stochastic blocks are shown to be consistent with fitted surrogates, supporting trustworthy confidence estimation. Incremental improvements to individual block implementation sets propagate to the global Pareto front without structural diagram changes, facilitating modular algorithmic upgrades.

Figure 11: Pareto front evolution under expanded implementation sets for chip mapping, demonstrating modularity and compositionality.

Practical and Theoretical Implications

The proposed framework realizes several critical advances:

• Formal uncertainty quantification: Confidence management as an explicit, continuously tunable resource enables rigorous reliability budgeting.
• Robust modularity: Interface-based MDPI decomposition allows independent block improvements—training surrogates, mapping solvers, fabrication yield models—without redesigning the full pipeline.
• Composition across abstraction levels: The order-theoretic structure supports integration from software to fabrication, scalable across hierarchical system designs.
• Algorithm–framework independence: Algorithmic improvements and surrogate replacements in any block immediately propagate in global resource–functionality trade-offs.

These properties position the methodology as a rigorous, extensible foundation for holistic hardware–software co-design.

Conclusion

The uncertainty-aware MDPI-based co-design framework unifies neural network, hardware mapping, fabrication, and computation resource planning within a principled compositional optimization structure. Core advances include explicit confidence management, modular block interchangeability, surrogate-based offline evaluation, and order-theoretic compositionality. Case studies validate end-to-end design recovery, trustworthy uncertainty propagation, and modular algorithmic upgrades. The approach is directly extensible to richer surrogate models, broader hardware platforms, hierarchical system co-design, and tighter EDA integration, with potential to catalyze further developments in AI and electronic design automation.