CPPL: A Circuit Prompt Programming Language

Abstract: LLMs have shown promise in register-transfer level (RTL) design automation, but direct RTL generation remains difficult to validate, optimize, and integrate with compiler-based hardware design flows. Hardware compiler infrastructures such as CIRCT provide typed intermediate representations, legality checks, and optimization passes, yet current LLMs struggle to emit raw compiler IR because of MLIR syntax, SSA discipline, dialect-specific operations, and strict width constraints. This paper presents CPPL, a compiler-mediated design framework that turns LLM-assisted hardware generation into a statically checkable frontend problem rather than an unconstrained RTL text-generation task. CPPL combines a Python frontend DSL for declaring module interfaces and hierarchy with CPPL IR, a JSON-based circuit IR designed to expose compiler-visible structure while remaining accessible to LLMs. The compiler infers operation widths from declared module ports, validates generated IR, checks hierarchy and port bindings, and deterministically lowers the result to CIRCT for synthesizable Verilog generation. On the RTLLM benchmark, CPPL improves functional correctness over direct Verilog and direct CIRCT IR generation, while CIRCT optimization reduces post-synthesis AIG node counts. These results show that a compiler-mediated interface can make LLM-assisted hardware design more reliable, analyzable, and amenable to backend optimization. CPPL is available at https://github.com/SawyDust1228/CPPL.

• The paper introduces CPPL, a compiler-mediated paradigm that uses a Python DSL and JSON IR to enforce strict type checking, SSA constraints, and hierarchical correctness.
• CPPL mitigates compositionality and syntax errors by guiding LLMs, achieving up to 0.768 functional pass@1 compared to steep drop-offs in direct CIRCT IR generation, as shown in RTLLM benchmarks.
• By integrating CIRCT optimizations, CPPL reduces synthesis resource usage by 16%, ensuring enhanced backend hardware quality and improved functional correctness.

CPPL: A Circuit Prompt Programming Language

Motivation and Problem Formulation

The utilization of LLMs for register-transfer level (RTL) hardware design automation has advanced significantly, but end-to-end RTL generation remains fundamentally unconstrained, presenting substantial challenges in validation, functional reasoning, interface consistency, and structural verifiability. Hardware compiler infrastructures such as CIRCT provide robust intermediate representations (IR), type checking, and canonical optimization passes, but LLMs fail to reliably emit MLIR-based IR due to SSA discipline, dialect boundaries, and strict type and width constraints. Large syntax and functional correctness gaps exist between direct Verilog generation and direct CIRCT IR generation by LLMs, as shown quantitatively in RTLLM benchmark evaluations—Verilog pass@1 consistently outpaces CIRCT IR pass@1 across all major LLM architectures (Figure 1).

Figure 1: The pass@1 score for syntax correctness is consistently higher on Verilog than CIRCT IR generation for all evaluated LLMs.

Intrinsic to this capability gap are compositionality problems: LLMs cannot reliably synthesize MLIR syntax tree structure, resolve width and type requirements, nor enforce SSA and dialect semantics without strong intermediate guidance, resulting in high rates of MLIR, CIRCT operation, and type errors (Figure 2).

Figure 2: The geometric average breakdown of error types in CIRCT IR across models on RTLLM, with CIRCT op errors being the largest contributor.

The CPPL Framework

CPPL is introduced as a compiler-mediated LLM hardware generation paradigm that inserts a statically checkable, LLM-friendly frontend prior to CIRCT IR codegen. The framework (Figure 3) consists of three main layers:

Figure 3: Overview of the CPPL framework, showing Python DSL frontend, JSON IR, and compiler-mediated program flow into CIRCT IR and Verilog.

1. Python-based Frontend DSL: Designers specify hardware modules, interfaces, and hierarchy using a highly structured Python function-oriented DSL. Module I/O interfaces are declared at the type-level, with bitwidths enforced at the type signature, ensuring explicitness.
2. JSON-based CPPL IR: Implementation intent is translated by LLMs into a machine-enforced JSON IR schema with explicit SSA values, port maps, and operation structure aligned with hardware semantics, but abstracting away CIRCT/MLIR syntax.
3. Compiler Validation and Deterministic Lowering: The CPPL compiler performs static syntax/width/type validation, interface and hierarchy preservation, dead code elimination, and combinational loop checking. Legal CPPL IR is deterministically lowered to CIRCT IR and, via CIRCT, to synthesizable Verilog for toolchain compatibility and hardware synthesis.

   Figure 4: CPPL integrates LLM generation with a compiler-mediated circuit IR path, enforcing checkability and enabling optimization.

Structural Semantics, Type Inference, and Hierarchy Preservation

CPPL enforces that explicit module interface and instance hierarchy declared in the frontend DSL is deterministically preserved in the lowered IR. This is formalized as an isomorphism between the frontend module/instance syntax tree and the IR hierarchy, maintained through compilation. Operation widths and types are inferred via declarative rules ensuring SSA graph correctness, preventing width mismatches and invalid hardware connections. The legal output path is thus strictly narrower and more structured than end-to-end natural language to RTL systems.

Evaluation: Syntax and Functional Correctness

Rigorous benchmarking on RTLLM demonstrates CPPL’s impact. Direct Verilog generation achieves high syntax pass@1 rates ($>0.9$ for top models) but suffers significant functional correctness degradation (as much as a $15{-}25\%$ gap between syntax and functional pass@1, Table VI). Direct CIRCT IR generation yields even larger drop-offs (e.g., Qwen-3.6-plus: $0.918$ syntax pass@1 for Verilog vs. $0.093$ for CIRCT IR, Table VII). Error analysis reveals CIRCT dialect misuse and type errors as the worst offenders.

By contrast, CPPL-based hardware generation consistently achieves higher Verilog functionality pass@1, systematically closing the gap between syntactic and semantic correctness (Table VIII). Notably, models incapable of generating legal CIRCT IR directly (e.g., Qwen-3.6-plus with $0.082$ CIRCT IR functional pass@1) are able to obtain strong functional performance (up to $0.768$ pass@1) under the CPPL path.

Backend Optimization and Hardware Quality

Because CIRCT is engaged in the code generation pipeline, classic logic synthesis optimizations (constant folding, DCE, CSE, etc.) are automatically applied prior to Verilog emission. Synthesis experiments using Yosys show that post-aigmap AIG node count is consistently reduced by CIRCT optimizations, achieving a $16\%$ average reduction across RTLLM designs (Table IX), highlighting the practical resource and quality advantages of compiler mediation.

Implications and Future Developments

CPPL validates the hypothesis that LLM4RTL performance is tightly bottlenecked by the lack of structured, statically checkable IR targets. LLM middleware that exposes only untyped, unconstrained natural language or raw RTL generation is suboptimal for rigorous hardware co-design. CPPL demonstrates that by decoupling interface/hierarchy specification and constraining LLM output to a JSON circuit IR with strong compiler mediation, reliability and compositionality are substantially improved.

This paradigm is complementary to and stackable with future advances such as LLM fine-tuning for hardware IR, retrieval-augmented generation of intermediary circuit fragments, and agent-based multi-stage prompt/program synthesis pipelines. Multi-pass repair, assertion synthesis, and EDA/DFT integration pipelines may similarly benefit from extending the statically checked, compiler-mediated approach. As hardware compilers (e.g., CIRCT/MLIR) expand dialect coverage and typing, such compiler mediation will be required for higher-assurance LLM-driven hardware generation flows.

Conclusion

CPPL establishes a new pathway for LLM-assisted hardware design. By introducing a compiler-mediated prompt programming language and circuit IR, the framework enables robust, analyzable, and optimizable hardware generation workflows, yielding significant improvements in both functional correctness and backend logic quality over direct generation baselines. This work substantiates the importance of compiler infrastructure integration in reliable LLM4RTL deployment and anticipates further synergies between prompt-programming, static IR validation, and EDA toolchains.

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Reference:

CPPL: A Circuit Prompt Programming Language (2605.17892)