Integrated photonic computing: towards high-dimensional information processing

Abstract: The rapid growth of artificial intelligence, coupled with the slowing of Moore's law, is straining computing infrastructure, as CMOS electronics face inherent limits in bandwidth, energy efficiency, and parallelism. Integrated photonic computing encodes and processes information using the phase, amplitude, spatial modes, wavelength channels, and polarisation of guided optical fields, offering a scalable and energy-efficient route beyond charge-based signalling. Here, we review on-chip photonic computing, emphasising the progression from low-dimensional to high-dimensional architectures. At the foundational level, low-dimensional approaches manipulate the phase and amplitude of guided light through Mach-Zehnder interferometers, diffractive structures, microring resonators, and absorptive elements, forming a programmable basis for optical matrix-vector multiplication. Crucially, high-dimensional architectures exploit spatial modes and wavelength channels to carry multiple independent data streams through a single waveguide, achieving higher throughput with moderate hardware overhead. Practical deployment, however, demands more than device innovation. We examine how system-level techniques, from time-wavelength interleaving to hardware-aware training, address energy efficiency, precision, and algorithm-hardware co-design. Five challenges nevertheless remain: electro-optic conversion efficiency, computing parallelism, spatial integration, reconfigurability, and robustness. We highlight emerging topological structures, such as optical skyrmions, as a promising route to fault-tolerant, topologically protected encoding that exploits the largely untapped polarisation degree of freedom. We argue that, by embracing the higher dimensionality of light, photonic computing can offer not merely an incremental improvement but a new paradigm for high-performance, energy-efficient information processing.

• The paper introduces a comprehensive review of photonic computing that leverages light's phase, amplitude, and spatial modes for scalable AI processing.
• It details innovative device-level techniques, including MZIs, microring resonators, and phase-change materials, achieving performance up to 65.5 TOPS with sub-10 ns latency.
• It emphasizes system-level co-design and challenges such as electro-optic conversion and integration scalability, paving the way for robust, fault-tolerant photonic accelerators.

Integrated Photonic Computing: High-Dimensional Architectures for Information Processing

Introduction

The escalation in AI workloads and the deceleration of Moore’s Law have rendered classical CMOS-based architectures insufficient in meeting contemporary demands for bandwidth, latency, energy efficiency, and parallelism. Integrated photonic computing (IPC) emerges as a compelling alternative, utilizing the intrinsic properties of light—namely, phase, amplitude, polarization, spatial modes, and wavelength—to encode and process information at scale, circumventing the fundamental limitations of electron-based circuits. This paper provides a comprehensive review focusing on the architectural progression of on-chip photonic computing, from low-dimensional matrix-vector multiplication (MVM) primitives to sophisticated high-dimensional systems, with critical analysis of device-level and system-level co-design for practical AI acceleration (2605.14690).

Physical Principles and Device Architectures

At the physical layer, IPC manipulates the fundamental degrees of freedom of light, which can be broadly categorized as follows:

• Phase and Amplitude Modulation: Foundational photonic processors employ Mach-Zehnder Interferometers (MZIs), microring resonators (MRRs), and absorptive elements for individual channel control. MZIs enable universal linear optical transformations and are routinely used in large-scale, programmable mesh networks [48, 54, 56], while diffractive structures offer scalable implementations with linear hardware complexity. MRRs provide compact, efficient amplitude modulation and facilitate wavelength-division multiplexing (WDM).
• Absorptive Structures and Phase-Change Materials (PCMs): Absorptive modulators based on tunable carrier absorption (PIN diodes) and nonvolatile PCMs are critical for analog weight encoding in photonic tensor cores, supporting dense crossbar configurations for parallel MVM [75, 80]. PCM-based systems achieve high analog contrast, suited for scalable all-optical inference and in situ on-chip training.

The high degree of device maturity is reflected in demonstrated photonic processors attaining up to 65.5 TOPS, with latency below 10 ns, and competitive precision on DNNs such as ResNet and BERT [56].

High-Dimensional Photonic Computing

Scaling beyond one-dimensional signal channels, high-dimensional IPC leverages the multidimensionality of light for exponential increases in information throughput:

• Mode-Division Multiplexing (MDM): Information is encoded in transverse spatial eigenmodes. On-chip MDM systems support simultaneous, non-interfering computation across multiple modes, achieving channel scaling without additional waveguides or hardware replication [84, 87]. Practical demonstrations currently support up to 4-8 modes per waveguide, with ongoing advances targeting increased mode counts via crosstalk mitigation.
• Wavelength-Division Multiplexing (WDM): WDM exploits the optical spectrum, utilizing frequency combs to encode multiple data streams across tens to hundreds of wavelengths. State-of-the-art WDM photonic tensor cores have demonstrated throughput exceeding 2 Tera-MAC/s at 17 fJ/MAC using PCM arrays. Combining MDM and WDM (hybrid multiplexing) further enhances channel density and efficiency [30, 91].
• Polarization and Topological Degrees of Freedom: Polarization remains underutilized but offers an additional binary channel per waveguide. More substantially, topological encoding (e.g., optical skyrmions) unlocks robust fault tolerance, resistance to fabrication variance, and new forms of digital logic within photonic platforms [117, 119].

Notably, these multidimensional approaches allow for parallelization factors unattainable in classical electrical interconnects, with throughput improvements directly proportional to the number of orthogonal channels exploited.

System-Level Optimization

Device engineering alone is insufficient for practical, deployable photonic AI accelerators. Critical system-level co-design includes:

• Time-Wavelength Interleaving: Decomposes high-rate data streams across multiple wavelengths and temporal slots, allowing use of lower-power, lower-speed DACs and maximizing overall throughput without linear increases in energy cost [95].
• Amortized and Delocalized Computation: Server-client architectures enable weight sharing and optical accumulation, achieving sub-photon energy costs per MAC operation in distributed applications [96].
• Coherent Detection: Homodyne and heterodyne detection preserve amplitude and phase information, relaxing the constraints of non-negative real-valued computation and natively supporting complex-valued operations [100].
• Efficient Learning Methods and Hardware-Aware Training: Forward-mode and in situ backpropagation shift gradient evaluation into the optical domain, minimizing external computational dependency. Hardware-aware regularization ensures robust inference in the presence of thermal and fabrication drift, a key consideration for analog photonic neural networks [102, 105].

Challenges and Research Directions

Despite rapid advances, IPC must contend with key technical hurdles:

• Electro-Optic Conversion Overhead: ADCs/DACs at the interface between electronics and photonics remain the primary energy bottleneck. Novel architectures that minimize conversion steps or adopt fully analog/optical interconnects are essential for achieving projected attojoule-per-operation targets [41, 110].
• Scalability and Integration: Planar silicon photonic integration is constrained by chip area and lacks vertical (3D) interconnects. 3D photonic integration, leveraging direct laser writing and multilayer lithography, provides routes towards higher density and vertically integrated networks [121, 123].
• Reconfigurability and Robustness: Fast, power-efficient, low-crosstalk modulators (e.g., hybrid LiNbO3 electro-optic, MEMS, and acousto-optic) remain an active research area. Topological encoding promises error-resilient logic and memory, but practical deployment demands further miniaturization and seamless integration with existing platforms.
• Algorithm-Hardware Co-Design: As system scale increases, robust algorithms capable of exploiting hardware non-idealities and maximizing parallelism become imperative, particularly for large-scale AI training and inference regimes.

Implications and Future Prospects

IPC represents a paradigm shift for high-performance and energy-constrained computing scenarios, such as AI inference, DNN training, and high-throughput data centers. The exploitation of high-dimensional photonic degrees of freedom—especially hybrid MDM/WDM and topologically protected states—offers scalability and efficiency unattainable in CMOS-based systems. Continued advances in materials, device architectures, 3D integration, and cross-layer algorithm co-design are likely to catalyze the emergence of universal, fault-tolerant, and sustainable photonic accelerators for next-generation AI and scientific computing.

Conclusion

Integrated photonic computing, by leveraging the deep multidimensionality of light, establishes a robust hardware foundation for the continued scaling of AI workloads beyond the limits of conventional electronics. Progress in high-dimensional multiplexing, system-level energy optimization, and topological fault tolerance signifies that photonic architectures are poised not for incremental progress but for establishing fundamentally new paradigms in computation. Challenges remain at the interfaces (electro-optic efficiency), in integration (3D scaling), and in the exploitation of underutilized optical degrees of freedom, but the trajectory outlined in this review underscores the centrality of photonic information processing in the era of post-Moore AI growth (2605.14690).