Factoring $2048$ bit RSA integers with a half-million-qubit modular atomic processor

Abstract: Shor's algorithm is one of the most promising applications of quantum computers. However, since $\sim 10^6$ physical qubits are believed to be required for established approaches, the algorithm will need to be distributed across many modules. In this paper, we provide a distributed compilation of Shor's algorithm on a modular atomic processor. We present an end-to-end compilation and optimization strategy that focuses on the interplay between the inter-module communication and the intra-module clock rate. With a half-million-qubit modular atomic processor with a communication rate of $10^5$ Bell pairs per second and a measurement time of 1 ms in a CPU-inspired architecture, we demonstrate that 2048-bit RSA integers can be factored in only 16\% more time than a single-module architecture. Our work presents the first end-to-end analysis and simulation of large-scale integer factorization on modular atomic hardware and it provides a blueprint for the future design of other large-scale modular algorithms.

• The paper presents a distributed implementation of Shor’s algorithm to factor 2048-bit RSA integers using a half-million-qubit modular atomic processor.
• It decomposes modular exponentiation into efficient routines with locality-aware protocols that significantly reduce non-local communication overhead.
• Strong scaling analysis shows that realistic hardware configurations can achieve RSA-2048 factorization in under a year, validating hybrid memory-logic co-design principles.

Distributed Shor’s Algorithm with Modular Atomic Processors for RSA-2048 Factorization

Introduction and Context

The paper "Factoring $2048$ bit RSA integers with a half-million-qubit modular atomic processor" (2605.03951) presents an end-to-end compilation, resource analysis, and architectural synthesis of Shor’s algorithm for integer factorization at the RSA-2048 scale, implemented on a modular neutral atom platform. The authors devise distributed, hardware-aware protocols that target realistic, near-term atomic array architectures, incorporating both code switching between qLDPC and surface codes and a nuanced treatment of inter-module communication costs and atom motion limits. The work advances previous efforts by rigorously modeling the performance, overheads, dataflow, and strong scaling of distributed Shor’s algorithm (DShor), providing concrete design blueprints and performance predictions at practical resource scales.

Hardware-Algorithm Co-Design for DShor

The modular processor architecture is constructed around a division of labor between memory modules—optimizing dense, largely inactive storage with qLDPC codes—and quantum processing unit (QPU) modules—optimized for fast, local Clifford and non-Clifford logic with surface codes. The architectural design aligns with well-understood hardware constraints in neutral atom arrays, including qubit connectivity stemming from tweezer and cavity arrangements, atom movement constraints, and the cost asymmetry between local and non-local gates.

Figure 1: Architecture of the DShor algorithm showing distributed modular exponentiations and explicit modular QPU internals, including code-specific cache, CCX (Toffoli) factories, communication arrays, and detailed patch organization.

A critical contribution is the compilation of modular exponentiation—the computational bottleneck of Shor’s algorithm—into a resource-efficient, distributed structure. Modular exponentiation is hashed into windowed residue arithmetic, minimizing qubit footprint by using short discrete logarithms [Gidney2025], and fundamental arithmetic operations are further decomposed to efficient primitive routines of addition, loading, and conditional reset, exploiting nearest-neighbor interactions for communication locality.

Algorithmic Structure and Fundamental Operations

The overall algorithmic workflow splits Shor’s algorithm into five sequential phases: (1) memory loading, (2) qubit compression, (3) modular exponentiation, (4) memory accumulation, and (5) state cleaning. Each modular exponentiation is explicitly decomposed to a circuit-level representation of addition and loading routines, all of which are distributed across QPUs and orchestrated with minimal non-local traffic.

Figure 2: Schematic decomposition of DShor, including memory-QPU interactions, modular exponentiation expansion, and verification of circuit trajectories within the custom simulator.

A core result is that addition ladders—used extensively for modular arithmetic—require only ripple-based, local communication between adjacent modules to propagate overflow information. The only non-local communication involves the relatively infrequent operations of memory loading and result accumulation.

Figure 3: Distribution of fundamental operations (loading, adding, cleaning), demonstrating the GHZ-broadcast method for loading and ripple-style overflow propagation for addition, ensuring locality across QPUs.

Resource Scaling, Performance, and Communication Analysis

A detailed simulation framework is developed to instantiate and verify circuits for DShor at the scale required for RSA-2048. The strong scaling analysis explores architectures with varying QPU module counts, quantifies the impact of inter-module Bell pair rates, and benchmarks circuit times with respect to both local gate and measurement rates. The findings are definitive:

• At $p_p=10^{-3}$, with a communication rate of $10^5$ Bell pairs/sec and a measurement time of 1 ms, the DShor architecture with 6 QPUs and 1 memory module requires roughly $3.7\times10^5$ physical qubits for the QPU modules and $10^5$ for memory.
• The total runtime to achieve a single, logical, error-free factoring shot at RSA-2048 is $190.4$ days—within $16\%$ of the single-module reference time, indicating a minimal penalty from distributed execution provided realistic communication rates are achieved.

  Figure 4: DShor T-gate usage and inter-module communication analysis across QPU counts, showing the highly local nature of most traffic and identifying the router QPU as the main communication/Toffoli bottleneck.

  

  Figure 5: Performance scaling of DShor including circuit time versus inter-module delay, QPU module qubit occupation, and the shifting boundary for “free modularization” as measurement times vary.

Contrary to some earlier expectations, most of the communication overhead is local, with non-local communications under 5% in standard configurations. This is achieved through decomposition and careful assignment of intermediate results.

Architectural Extensions and Alternative Interconnects

The paper not only explores photonic interconnect architectures but also provides detailed blueprints for dynamic array-based modularization. Mechanical motion of dynamic tweezer arrays between static QPU modules allows bandwidths that surpass even optimistic cavity-based photonic predictions, at the cost of added engineering complexity and latency associated with mechanical motion.

Figure 6: Modular atomic processors interconnected by dynamic arrays, providing an alternative to photonic links and enabling high spatial bandwidth.

Figure 7: Schematic circuit for dynamic array-based modular loading, exploiting Bucket-Brigade and drive-by Rydberg gates for parallel, high-bandwidth transfers.

The performance penalty for dynamic arrays—primarily from acceleration/deceleration cycles—is characterized, and throughput gains are modeled using explicit mechanical parameters (max jerk, acceleration). The authors demonstrate that bandwidth and latency targets compatible with $\sim30-100$ day runtime for RSA-2048 are feasible within mechanical limits of commercial motion hardware.

Implications for Large-Scale Quantum Architectures

By extending the distributed model to QGPU-style architectures with $\sim100$ modules and aggressive code distance reduction (e.g., $d=9$), the work demonstrates that further parallelism and simultaneous modular exponentiation can push factoring times below 5 days at the expense of increased total qubit count ($p_p=10^{-3}$0 million qubits). However, communication remains the bottleneck for shot-parallel strategies, and the details of memory control and code conversion become critical.

Figure 8: QGPU architecture variants and circuit time reduction versus scaling parameter $p_p=10^{-3}$1, highlighting the tradeoff between increased processor parallelism and memory demands.

Verification, Compilation Optimizations, and Hardware Nuances

A custom Shor’s simulator is tightly integrated with the circuit compiler, tracking Hilbert-space trajectories and measurement-induced phases for resource estimation and verification. Practical protocols are introduced for qubit reallocation and code conversion, tightly coupled with atom-transport control strategies and hardware constraints.

Conclusion

This work presents the most concrete, comprehensive, and nuanced blueprint for modular, large-scale Shor’s algorithm deployment to date, targeting neutral atom hardware and realistic error rates. It demonstrates, via detailed simulation and mapping to contemporary experimental parameters, that integer factorization at the RSA-2048 scale is achievable in under a year with a half-million-qubit modular atomic architecture, and with minimal performance penalty compared to an ideal monolithic processor.

Key implications include validation of hybrid memory-logic code separation, explicit evidence that locality-aware compilation drastically contains communication overhead, and strong numerical support for the assertion that modular neutral atom processors enable utility-scale quantum algorithms at realistic hardware scales. These results inform both immediate experimental design and future architectural strategies as high-rate codes and improved decoders are realized.

Outlook

The presented methods—spanning circuit compilation, dataflow mapping, hardware-software co-optimization, and strong scaling—are likely extensible to broader classes of modular algorithms. The demonstrated modular decomposition, intra-module and inter-module orchestration, and communication-cost mitigation will be foundational in the design of quantum processors for both cryptographic and non-cryptographic applications as neutral atom arrays, error correction schemes, and integration technologies mature (2605.03951).

Figure 9: Illustration of the DShor estimation methodology, showing explicit buffer movement, trajectory tracking, circuit evolution, and resource estimation for the primary algorithmic modules.