Space-Time Tradeoffs of Pauli-Based Computation in Distributed qLDPC Architectures

Abstract: Pauli-based computation (PBC) provides a universal framework for executing fault-tolerant quantum algorithms using Pauli measurements and magic states. In monolithic architectures, the serialized nature of PBC directly ties runtime to a circuit's T-gate count, making it slow on metrics like circuit depth. However, in distributed quantum computing (DQC), the primary bottleneck is remote Bell pair generation. We investigate the tradeoff between error-correcting code block size and execution time of PBC within the Q-Fly architecture at intermediate scale, limiting individual node capacities to reflect near-term constraints while supplying abundant network nodes to minimize routing and compilation effects. We find that large qLDPC code blocks outperform the surface code baseline in terms of execution time by up to an order of magnitude when evaluated against quantum optimization algorithms. By moving groups of qubits to free nodes to bypass the sequential bottleneck of PBC, the large-block architecture minimizes network operations and achieves faster overall execution. This demonstrates that PBC is a competitive model in the distributed regime, establishing it as a practical compilation baseline for qLDPC systems before invoking more efficient transversal or homological gates.

• The paper presents a comprehensive analysis of space-time tradeoffs in fault-tolerant quantum computing using a Pauli-based paradigm on distributed qLDPC architectures.
• It employs the hierarchical Q-Fly topology and advanced circuit optimizations, such as QCLA-based phase synthesis and fan-out techniques, to significantly reduce temporal depth and enhance parallel execution.
• The study demonstrates that architecture-circuit co-design can yield up to an order of magnitude improvement in runtime over traditional surface code approaches while respecting hardware constraints.

Space-Time Tradeoffs of Pauli-Based Computation in Distributed qLDPC Architectures

Architectural Foundations and Motivations

This paper systematically analyzes the space-time tradeoffs in fault-tolerant quantum computation (FTQC), specifically targeting distributed quantum computing (DQC) with high-rate quantum LDPC (qLDPC) codes. The research adopts Pauli-based computation (PBC) as the computational paradigm due to its universality and practical alignment with measurement-based execution, particularly in distributed settings where interconnect speed is the dominant operational bottleneck rather than circuit depth.

The study employs the hierarchical Q-Fly architecture, a dragonfly-inspired network topology, which is characterized by scalable connectivity with minimized switch sizes and robust bandwidth. This topology is parameterized by the number of groups, nodes per group, and a circulant chordal inter-group connectivity. The hardware baseline enforces realistic constraints, such as fixed node memory, bounded switch hops, and independent local access to magic states, mapping directly onto near-term technological limitations.

Figure 1: Example of a Q-Fly architecture with five groups, each composed of four quantum nodes, an optical switch, and a pool of Bell state analyzers, illustrating the hierarchical connectivity.

Algorithmic Scope and Circuit Requirements

The research focuses on two optimization algorithms with practical relevance: quantum approximate optimization algorithm (QAOA) and decoded quantum interferometry (DQI). For QAOA, the phase oracle involves clause evaluation via multi-controlled Toffoli (MCT) gates, demanding generalized Boolean AND circuits and single-qubit rotation synthesis. DQI, on the other hand, implements amplitude encoding, Dicke state preparation, coherent LDPC decoding, and binary arithmetic (primarily CNOTs), targeting Max-LINSAT instances.

Both algorithms are selected for their relatively shallow circuit depths (scaling linearly with input size) and recent empirical evidence for quantum advantage over classical heuristics. The study deliberately avoids resource-heavy cryptanalytic benchmarks to maintain relevance to near-term FTQC applications.

Space-Time Circuit Optimization Techniques

Parallelizable Arithmetic and Fan-Out

The paper analyzes two quantum addition strategies: the Gidney ripple-carry adder and the Sklansky prefix-tree QCLA. The QCLA leverages fan-out primitives and block-based carry propagation, which can be efficiently mapped to the Q-Fly topology, yielding significant reductions in temporal depth compared to sequential adders. This enables the architecture to exploit spatial locality for parallel execution.

Single-Qubit Rotation Synthesis

Rotation gates are synthesized using either gridsynth (Clifford+$T$) or phase-gradient techniques with QCLA, with a detailed comparison of their temporal scaling as a function of target accuracy. The crossover point is computed explicitly, showing that QCLA-based phase gradient methods outperform gridsynth for bit-precision exceeding approximately 44 bits at realistic interconnect speeds. This analysis guides the selection of rotation strategies in circuit design.

Controlled Rotations, Dicke State Preparation, and Coherent Decoding

Multi-controlled rotations are constructed via temporary-AND compute-uncompute (TACU) gadgets, optimizing the non-Clifford depth. Dicke states are prepared using the recursive weight distribution block (WDB) approach, balancing circuit depth against arithmetic overhead and inter-node communication. The resource estimation for Dicke state generation quantifies both controlled rotation and Toffoli layers, parametrized by Hamming weight and register size.

Resource Estimation and Empirical Results

Comprehensive temporal resource estimates are computed for all core subroutines and both algorithms, explicitly accounting for spatial arrangement, routing latency, and cross-node communication. The QAOA implementation for 8-SAT ($n=64$, $m=11,264$) and DQI for Max-LINSAT ($n=50$, $m=200$) are benchmarked with 64-bit precision.

Key findings reveal that, for conservative interconnect speeds ($T_{\rm Bell}=10$ cycles), a single QAOA iteration completes in $<50,000$ cycles using qLDPC codes and the Q-Fly architecture, whereas the surface code active volume model requires nearly two million cycles, given identical physical resources. Dicke state preparation and quantum arithmetic dominate the sequential runtime of DQI, but remain favorable relative to surface code baselines due to parallelized logical capacity.

Comparative Analysis and Implications

The paper establishes that moving from surface code to high-rate qLDPC codes, and designing circuits with architectural awareness, unlocks substantial acceleration—up to an order of magnitude in execution time—without increasing the physical footprint. The analysis rigorously normalizes all estimates by logical cycle counts and accounts for the strictest hardware constraints, revealing the fundamental limits imposed by space-time tradeoffs in the distributed paradigm.

The Q-Fly topology is shown to offer optimal routing with minimized switch and entanglement overhead, significantly outperforming monolithic or deep-tiered alternatives such as fat-tree or Clos networks. The architecture enables aggressive parallelization and reduces sequential bottlenecks inherent in PBC, making it a practical compilation baseline for qLDPC systems before invoking transversal or homological gates.

Future Directions and Theoretical Outlook

The results imply that future quantum processors should emphasize parallel logical capacity and topology-aware circuit synthesis to fully exploit distributed architectures. Further advances may explore adaptive circuit partitioning, hybrid architectures combining qLDPC and surface code patches, and enhanced protocols for remote entanglement generation and resource distillation. Algorithmic co-design that factors in physical layout, code structure, and routing is highlighted as an essential direction for scalable FTQC.

Conclusion

This work demonstrates that Pauli-based computation over high-rate qLDPC codes within hierarchical distributed quantum architectures, such as the Q-Fly model, delivers substantial runtime improvements compared to surface code baselines, given identical hardware resources. By exploiting parallelism, optimal routing, and circuit design tailored to architecture, the study highlights the critical role of space-time tradeoffs in achieving practical quantum advantage. The findings inform future strategies for architecture-circuit co-design, prioritizing logical abundance and routing efficiency as key criteria for quantum computation in the distributed regime.