Near-Term Reduction in Nonlocal Gate Count from Distributed Logical Qubits

Abstract: Modular quantum computing architectures require error correction schemes that remain effective in the presence of noisy inter-processor operations. As such, minimizing the number of such operations on logical circuits partitioned across quantum processors is a primary objective of distributed quantum computing. In this work, we develop basic techniques for qubit allocation using an exemplar color code family and explore generalizations to other color codes. In particular, we show that a 10% reduction in processor-nonlocal gates is achievable in a setting where syndrome extraction occurs after every logical gate, as in today's devices, and that this scales to significantly greater advantages in the multi-qubit case. We also explore methods of achieving universal gate sets efficiently in this distributed logical setting and evaluate the trade-offs of multiple approaches such as magic state distillation, code switching, and a new method based on logical swaps. Finally, we discuss some considerations for an allocation algorithm for these architectures to perform scalably and connect it to existing work on quantum circuit partitions.

• The paper shows that distributing logical qubits across processors reduces nonlocal gate overhead by approximately 10% using 2D color codes.
• The methodology leverages gate teleportation and multilevel circuit partitioning to optimize syndrome extraction and balance qubit allocation constraints.
• It further examines fault-tolerant techniques such as magic state distillation, code switching, and dynamic logical swaps to achieve universal gate sets in distributed architectures.

Near-Term Reduction in Nonlocal Gate Count from Distributed Logical Qubits

Overview

This paper investigates the reduction of processor-nonlocal (PNL) gate counts in distributed quantum computing architectures by leveraging logical qubits partitioned across multiple quantum processors. Using 2D color codes as a case study, the authors address the practical constraints of current platforms—especially the necessity of frequent syndrome extraction and strict qubit allocation—and analyze how distributing logical qubits impacts PNL gate overhead. The paper further evaluates techniques for fault-tolerant universality, such as magic state distillation and code switching, as well as partitioning strategies that optimize PNL gate reductions in both small- and large-scale architectures.

Distributed Logical Qubits and Processor-Nonlocal Operations

The central motivation is to mitigate the bottleneck imposed by low-fidelity and slow inter-processor links in near-term distributed quantum computers. Whereas fully transversal logical operations often demand processor-nonlocal (PNL) gates, distributing a logical qubit across processors shifts the nonlocality from gate execution to stabilizer measurement. This is typically realized via gate teleportation (see Figure 1), with the PNL gate count scaling dictated by how the logical code is partitioned.

Figure 1: Distributed logical qubits require PNL stabilizer measurements as opposed to PNL transversal gate implementations (top). In this work, these PNL gates are mainly implemented by gate teleportation (bottom, $\ket{\psi}$ as control, $\ket{\phi}$ as target).

Qubit Allocation in 2D Color Codes

By focusing on the [[31,1,7]] 4.8.8 color code, the authors demonstrate that a strict, balanced bipartitioning across two processors achieves a 10% reduction in PNL gates per logical gate (28 versus 31 gates) without relaxing the physical qubit per-processor constraint. This advantage generalizes for larger code distances in the 4.8.8 color code family, whereas the 6.6.6 family only gains benefit at substantially larger code distances due to increased cut stabilizer weights.

Figure 2: The cut which allows an equal partition of the $d=7$ 4.8.8 color code; only 28 PNL gates are required, compared to 31 needed for processor-local implementations.

Figure 3: In the two-processor (two logical qubit) case, the 4.8.8 code family shows PNL reductions at and above $d=7$; the trend is less pronounced or delayed for the 6.6.6 family due to code geometry.

The scaling is linear in code distance for PNL gates arising from stabilizer splits, but quadratic in distance for nonlocal gates required by transversal gate execution in local codes. Thus, with sufficiently large distance or circuit depth, distributed allocation offers increasingly substantial PNL reductions.

Extension to Multiple Processors

While intuition suggests that further partitioning among more processors should compound PNL gate reductions, each additional partition increases the number of nonlocal stabilizer measurements per round. The benefit, therefore, only emerges for higher code distances, with the minimum code distance for PNL gate reduction scaling approximately linearly with processor count.

Figure 4: As logical qubits are split across more processors, the code distance required for overall PNL reduction increases roughly linearly with the number of processors.

Fault-Tolerant Universal Gate Sets in Distributed Architectures

Realizing Clifford+T universality within a distributed logical qubit paradigm is nontrivial due to the restrictions of the Eastin-Knill theorem. The paper thoroughly examines three universal gate construction techniques, evaluating scaling and resource trade-offs for distributed codes.

Magic State Distillation (MSD)

When magic state distillation is co-distributed with computational logical qubits, the per-processor qubit burden is reduced while keeping distillation and injection operations processor-local. This architecture allows only $O(d)$ PNL gates in syndrome extraction, compared to $O(d^2)$ for non-distributed approaches; however, the exponential scaling of required distillation rounds limits the advantage to near-term, small circuits.

Figure 5: In magic state injection, a high-fidelity magic state is prepared and then consumed to apply a $T$ gate via a dedicated injection gadget.

Figure 6: Fully distributed distillation and injection reduce per-processor qubit counts and limit total PNL gates to $O(d)$ for small circuits.

Figure 7: Only three logical qubits per processor and $O(d)$ PNL gates suffice with a fully distributed magic state distillation approach.

Code Switching

Switching between 2D self-dual and 3D triorthogonal codes permits transversal non-Clifford gates but introduces substantial stabilizer measurement overhead due to the high cut weight in 3D codes. While ancillary swapping/teleportation can reduce the PNL gate cost, the scaling remains $O(d^2)$ for realistic, equal-size partitions.

Figure 8: With both 3D and 2D codes split across processors, code switching can be implemented processor-locally, allowing qubit overhead reduction.

Figure 9: No advantage is found for code switching via distributed blocks with standard stabilizer measurement; ancilla swapping is required for improvement.

Dynamic Logical Swaps

By explicitly swapping logical ancilla and code qubits to gather them locally for chains of non-Clifford gates, PNL gate usage is drastically reduced at the expense of greater space overhead. This method is particularly beneficial for circuit segments that require repeated H-T alternations or high CNOT density.

Figure 10: Swapping or teleporting data and ancilla qubits to localize resources reduces total PNL gates when repeated switching or distillation is required.

Partitioning Algorithms and Circuit Allocation

To optimize for PNL gate reductions in general circuits and heterogeneously constrained architectures, the authors recommend multilevel circuit partitioning. The optimal partitioning depends on circuit structure, the ratio of different gate types, and processor size constraints. For circuits dominated by local two-qubit gates, large processor groups with minimal PNL interactions are preferred, whereas further subdivision only yields benefit when the distribution-induced stabilization cost does not surpass the locality gain.

Figure 11: A zero-cost circuit partitioned fully locally among two two-qubit processors as an illustration of optimal allocation for circuit structure.

The discussion highlights the nuanced trade-off: indiscriminate further partitioning can result in diminishing returns or even higher overall PNL gate costs due to increased stabilizer measurement overhead.

Implications and Future Directions

The analysis demonstrates concrete, practical PNL gate reductions of approximately 10% in current code and device regimes, and clarifies under which architectural and circuit-structural conditions such reductions scale favorably. These results are immediately relevant for near-term proof-of-principle experiments and early-stage distributed quantum processors, particularly where network constraints and qubit budgets are severe.

The extension to more general code families, the incorporation of advanced stabilizer measurement techniques (Floquetization, flag-based syndromes), and relaxed qubit allocation constraints represent important directions for further research. Additionally, integrating heterogeneous processor capabilities and developing partitioning algorithms aware of non-Clifford gate density will be essential for scalable fault-tolerant DQC.

Conclusion

This work rigorously quantifies the PNL gate savings achievable by distributing logical qubits across quantum processors, especially in 2D color codes, within strict qubit and syndrome extraction constraints. It elucidates the comparative performance of magic state distillation, code switching, and dynamic logical swaps for realizing universality under distributed allocation, providing guidance for practical near-term quantum processor network design and circuit compilation. The findings suggest significant, architecture-dependent reductions in PNL overheads are possible but must be balanced against circuit structure and required code distances. Future advances will hinge on code family generalization, improved stabilizer measurement, and topology-aware partitioning algorithms.