Defect-Adaptive Lattice Surgery on Irregular Boundary Surface-Code Patches

Abstract: Defect-adaptive surface-code methods have substantially advanced the construction of valid logical patches on imperfect hardware, but fault-tolerant computation also requires executable logical oper ations on the resulting irregular geometries. We formulate the seam-boundary defect problem: how to perform a lattice-surgery merge when the intended seam intersects deformed boundaries, disabled checks, and gauge-inferred super-stabilizers. We introduce a defect-adaptive lattice-surgery method that reconstructs the target joint logical parity from the seam-related measurements available on the irregular merged patch, together with constraints inherited from the separated pre-merge code space. The reconstruction is expressed as a compact GF(2) binary-support synthesis problem. If the requested parity is realizable, the solution gives an executable parity-extraction rule over raw, schedule-tagged gauge outcomes; otherwise, it certifies a parity-synthesis failure rather than conflat ing it with patch invalidity. The framework accommodates boundary data-qubit defects, seam-check ancilla defects, and gauge-inferred seam super-checks within a single synthesis layer. Circuit-level samples of the synthesized merge operation show improved compile yield, preserved effective dis tance, and only modest success-conditioned logical-error overhead relative to the defect-free merge reference; an explicit ZZ-merge sampling check confirms the expected transposed-geometry behav ior under the same success-conditioned observable construction. More broadly, the results identify certified parity synthesis as a compilation layer between defect-adaptive patch construction and executable fault-tolerant logical operations on imperfect surface-code hardware.

• The paper recasts defect-adaptive lattice surgery as a rigorous GF(2) parity-synthesis problem to extract logical parity from irregular surface-code patches.
• It employs a three-step pipeline—identifying available seam operators, certifying compatibility, and performing binary-support synthesis—to ensure successful parity measurement.
• Numerical results demonstrate substantial compile yield improvements (+14 to +24%) and minimal logical distance loss, validating its applicability in noisy quantum hardware.

Defect-Adaptive Lattice Surgery for Irregular Surface-Code Boundaries

Introduction and Context

Surface codes are prominent in quantum error correction (QEC) due to their high error thresholds and compatibility with two-dimensional nearest-neighbor architectures. However, physical qubit arrays in real hardware invariably suffer from static or dynamic defects, such as missing or inoperable data qubits, ancillas, or couplers. While recent progress has enabled robust logical patches via defect-adaptive constructions—employing local boundary deformations, redundant gauge checks, and super-stabilizers—these advances have focused on preserving static code spaces rather than supporting logical operations, which are essential for universal, fault-tolerant quantum computation.

This paper addresses the operational bottleneck of performing lattice-surgery merges on defect-adapted, irregular patches. The authors formalize the seam-boundary defect problem, articulating a necessity: when the intended merge seam intersects with deformed boundaries, broken checks, or when required information is accessible only through gauge-inferred super-stabilizers, native seam-based parity extraction is no longer reliable.

Problem Formulation and Framework

Lattice surgery on the surface code is a standard technique for implementing Clifford-group operations by merging and splitting patches, fundamentally relying on the activation and measurement of a seam—a set of local stabilizers whose joint measurement yields the desired logical parity (e.g., $X_L \otimes X_L$ or $Z_L \otimes Z_L$). In the presence of defects, the seam's geometry may be disrupted, certain checks may be irrecoverable, and the logical operators’ support may be significantly altered.

The core contribution is to recast defect-adaptive lattice surgery as a rigorous, layered parity-synthesis problem: For a given irregular patch configuration, the method determines, certifies, and constructs the executable logical parity observable realizable from the physically available seam-adapted measurements, incorporating constraints inherited from the separated pre-merge codespace.

Figure 1: Illustration of seam-boundary data-qubit defects that necessitate reconstruction of the seam region and corresponding effective checks for parity extraction.

This approach transforms ad hoc geometric patch repair into a formal synthesis problem on binary vector spaces over $\mathrm{GF}(2)$. If a requested parity is not realizable within the available measurement grammar, the approach certifies and reports parity-synthesis failure, distinguishing it from overall patch invalidity.

Technical Framework and Synthesis Procedure

Seam Family Construction and Admissibility

The synthesis proceeds via a three-step pipeline:

1. Identification of Available Seam Family: The procedure enumerates effective seam operators that are physically or logically accessible on the merged patch. This includes direct seam or boundary checks, as well as products of local gauge measurements that reconstruct effective super-checks.
2. Compatibility Certification: Utilizing algebraic tests, the method filters out seam candidates incompatible with the commutation relations imposed by residual opposite-type (i.e., $Z$-type for $X$ merges and vice versa) stabilizer constraints. Additionally, it prioritizes seam and gauge decompositions that preserve logical distance, excluding orientations that would induce unnecessary shrinking of the code distance.
3. Binary-Support Synthesis: The core certification reduces to a $\mathrm{GF}(2)$ row-space membership test. The desired joint logical parity is encoded as a binary vector, and the method tests whether it can be synthesized as a sum (mod 2) of allowable seam-family rows and residual same-type stabilizer constraints. If successful, the solution yields an explicit selector for which physical measurements (including schedule-tagged gauge outcomes) must be XOR'd to extract the logical parity.

Figure 2: Demonstration of ancilla-defect handling, where seam-check ancilla loss is mitigated by a support-preserving reconstruction via local gauge fragments and promoted super-stabilizers.

This algebraic viewpoint ensures modularity: the seam family and constraint structure are abstracted as incidence matrices, enabling rapid certification and compilation.

Numerical Results

Distance Preservation

Explicit simulations over ensembles of random defect fields and varying code distances ($d \in \{9,11,13,15,17\}$) demonstrate that seam-parity synthesis via fused super-checks and distance-aware gauge selection significantly mitigates geometric distance loss. The proposed method recovers instances that standard techniques (that remove broken rows without replacement) would discard, decreasing average logical distance loss (Figure 3 in the paper, not shown here).

Compile Yield

The method substantially increases compile yield—the probability that a requested parity measurement is realizable and executable on a given defect instance. Across all studied distances and for moderate defect rates (e.g., $q=1$–$2\%$), the additional recovery of seam rows via GF(2)-certified super-check reconstruction yields $+14$ to $Z_L \otimes Z_L$0 percentage points improvement over the standard baseline.

Figure 4: Compile yield improvement versus defect rate for the proposed method versus standard seam-handling; substantial gains are seen at all code distances.

Logical Error Rate

Using the SI1000-MR circuit-level noise model and minimum-weight matching decoding, the success-conditioned logical error rates (LER) for the synthesized merge operations closely track those of the defect-free reference. Overhead factors in LER are modest ($Z_L \otimes Z_L$1 at realistic physical error rates), corresponding to only 1–2% distance loss as measured in experiment, and, crucially, are achieved without global schedule expansion—most instances require minimal extra rounds due to localized gauge super-checks.

ZZ Merges and Consistency Check

Applying the framework to transposed geometry ($Z_L \otimes Z_L$2-type merges; i.e., running the same compilation in the $Z_L \otimes Z_L$3 boundary setting), the method preserves all compile-yield and LER benefits, confirming generality across seam types and symmetry.

Figure 5: Success-conditioned logical error rates for compiled defect-adaptive ZZ merges reflect consistency and scaling similar to the $Z_L \otimes Z_L$4-type seam case.

Theoretical and Practical Implications

By raising defect-adaptive operation synthesis to a certified algebraic layer, this framework decouples patch viability from parity realization: patch adaptation yields a valid, but possibly irregular, logical qubit; certified parity synthesis rigorously determines which operations can be executed and how.

This synthesis-centric perspective supports explicit failure semantics: parity-synthesis failure is reported as an independent outcome, facilitating more robust fault-tolerant software and compiler design, as realistic quantum processors will operate under varying defect configurations.

Moreover, the GF(2) synthesis abstraction provides a fertile foundation for compiling more complex logical primitives—multi-patch operations, batched merges, and Clifford gate scheduling—on irregular substrates, with the possibility of further extension to device-specific asymmetric defect statistics and more intricate stabilizer codes.

Future Directions

While focused on merge operations, the binary-support synthesis model is not limited to merges and can, in principle, be integrated with higher-level error-correction and compilation strategies. Future research should formalize the synthesis layer for operation sequences, optimize for hardware-adaptive gauge decompositions, and benchmark performance on experimental devices with realistic, non-uniform defect distributions.

Integration with modular control software (see [Lin et al., 2025]) and extension to magic-state distillation and injection protocols are both immediate, impactful directions, enabling practical deployment of scalable lattice-surgery-based quantum processors in the presence of hardware-induced irregularities.

Conclusion

This work advances defect-adaptive fault tolerance by introducing a rigorous, compiler-level parity synthesis layer for surface-code lattice surgery on irregular geometries. By decoupling logical operation synthesis from patch adaptation and providing explicit executable rules with provable realizability guarantees, the framework enhances both the theoretical understanding and practical robustness of fault-tolerant operations on defective hardware. The approach achieves superior compile yield and distance preservation, with modest logical error overhead, and defines a modular primitive foundational for scalable quantum control on near-term noisy devices.