Lattice Surgery Compilation Beyond the Surface Code

Abstract: Large-scale fault-tolerant quantum computation requires compiling logical circuits into physical operations tailored to a given architecture. Prior work addressing this challenge has mostly focused on the surface code and lattice surgery schemes. In this work, we broaden the scope by considering lattice surgery compilation for topological codes beyond the surface code. We begin by defining a code substrate - a blueprint for implementing topological codes and lattice surgery. We then abstract from the microscopic details and rephrase the compilation task as a mapping and routing problem on a macroscopic routing graph, potentially subject to substrate-specific constraints. We explore specific substrates and codes, including the color code and the folded surface code, providing detailed microscopic constructions. For the color code, we present numerical simulations analyzing how design choices at the microscopic and macroscopic levels affect the depth of compiled logical $\mathrm{CNOT}+\mathrm{T}$ circuits. An open-source code is available on GitHub https://github.com/cda-tum/mqt-qecc.

• The paper introduces a general framework for compiling quantum circuits with lattice surgery, extending fault-tolerant compilation beyond the surface code.
• It employs a two-level abstraction that separates detailed microscopic implementations from macroscopic routing and mapping optimizations.
• Numerical results on color code substrates reveal trade-offs between layout density, circuit parallelism, and T-gate overhead in quantum circuit compilation.

This paper introduces a general framework for compiling quantum circuits using lattice surgery, extending beyond the commonly studied surface code to other topological codes like the color code and the folded surface code. The goal is to translate logical quantum circuits (specifically Clifford+T gates) into sequences of physical operations suitable for fault-tolerant quantum computers built with qubits having geometrically local connectivity.

Two-Level Abstraction Framework

The core idea is a two-level abstraction:

1. Microscopic Level: This level deals with the specifics of the quantum error-correcting code and the hardware layout.
   • Code Substrate: A "code substrate" is defined as a tiling (e.g., hexagonal for the color code, square for the surface code) representing the physical layout and connectivity of qubits. It serves as a blueprint for embedding logical qubits and performing operations. Data qubits and stabilizer checks are associated with elements of this tiling (e.g., vertices and faces).
   • Logical Patches: The substrate is partitioned into distinct regions:
     • L: Patches encoding logical data qubits.
     • F: Patches hosting magic state factories for T gates.
     • A: The remaining area, further divided into A* (ancilla patches used in routing) and potentially other physical ancillas (A \ A*) needed for microscopic connections.
   • Snakes: These are paths of ancilla patches (A*) and potentially other physical ancillas on the substrate used to connect distant logical patches (data or ancilla) to perform lattice surgery (specifically, joint $Z_LZ_L$ or $X_LX_L$ measurements required for CNOT gates). The paper emphasizes constructing "distance-preserving snakes" to maintain fault tolerance during the merge/split operations.
2. Macroscopic Level: This level abstracts away the microscopic details.
   • Routing Graph (R): A coarse-grained graph is derived from the substrate layout. Its vertices represent the logical data patches (L), ancilla patches (A*), and magic state patches (F). Edges represent the possibility of performing lattice surgery (via snakes) between adjacent regions on the substrate. For both example substrates considered, this results in a hexagonal routing graph.
   • Compilation as Mapping and Routing: The compilation task becomes:
     • Mapping ($\Lambda^*$): Assigning logical qubit indices from the input circuit to the logical data vertices (V_L) in the routing graph.
     • Routing: Finding sequences of non-overlapping paths on the routing graph R to implement the CNOT and T gates of the input circuit. A path between two data vertices corresponds to allocating a snake and a logical ancilla patch on the substrate to perform a CNOT via lattice surgery. A path from a data vertex to a magic state vertex implements a T gate via injection. The objective is to minimize the total depth (number of sequential steps) of the scheduled lattice surgery operations.

Microscopic Implementations and Fault Tolerance

The paper details microscopic constructions for two specific substrates:

1. Color Code Substrate:
   • Uses a hexagonal tiling where triangular regions form distance-d logical color code patches.
   • Lattice surgery (specifically $Z_LZ_L$ merge) between adjacent patches uses "semitransparent domain walls" (STDWs) involving measuring specific intermediary stabilizers.
   • Distance-preserving snakes are constructed using the subsystem code formalism. The paper outlines how to define the gauge group G, stabilizer group S, and logical operators for the joint system (patches + snake) to show that the logical distance d is maintained during merge/split operations.
   • Crucially, it details how to identify the subset of stabilizer measurements (M) whose product yields the desired $Z_LZ_L$ (or $X_LX_L$) outcome, handling the geometry of the hexagonal lattice and STDWs. An automated method for constructing these stabilizers and the set M is provided in the associated code package.
2. Folded Surface Code Substrate:
   • Uses a square tiling. Logical data qubits are encoded in folded surface code patches, potentially arranged in pairs to hide the folding diagonal. This allows transversal single-qubit Cliffords and access to both $X_L$ and $Z_L$ on certain boundaries.
   • Snakes and logical ancilla patches use standard (non-folded) surface codes, possibly requiring a stacked 2D architecture or non-nearest-neighbor connectivity if projected onto a single layer.
   • The routing on the corresponding hexagonal graph R has specific constraints: because standard surface code patches only offer $X_L$ or $Z_L$ along a given boundary type, a valid path for a CNOT must be complex enough (containing edges of all three directions in the hexagonal graph) to allow placing the logical ancilla such that both $X_LX_L$ and $Z_LZ_L$ measurements are possible.
   • Distance-preserving snakes are again constructed using the subsystem code formalism, ensuring fault tolerance. A detail regarding potential stabilizer deformation for misaligned patches is mentioned. An automated construction method is also available.

Macroscopic Compilation Algorithms

1. Routing (Shortest-First VDP):
   • The problem of finding parallel, non-overlapping paths for gates in a given time step is formulated as a Vertex Disjoint Path (VDP) problem on the routing graph R.
   • A greedy algorithm is used:
     • Compute shortest valid paths (using Dijkstra, potentially adapted for substrate constraints like minimum length or required edge directions) for all required CNOTs/T-gates in the current layer of the logical circuit.
     • Select the overall shortest path, add it to the current time step's operations, and remove its vertices from the available graph R.
     • Repeat until no more non-overlapping paths can be found for the current layer.
   • Gates that couldn't be routed are "pushed" to the next time step, respecting dependencies.
   • T-gate routing involves finding paths to available magic state factory patches (V_F), considering their state availability based on a fixed reset time t.
2. Mapping Optimization (Hill Climbing):
   • The initial assignment ($\Lambda^*$) of logical qubits to patches significantly impacts routing efficiency.
   • A Hill Climbing metaheuristic optimizes this mapping:
     • Metric: Either a fast heuristic (counting crossings of shortest paths for all gates in the circuit) or the exact (but slower) compiled depth ($\Delta$) from the VDP solver.
     • Neighborhood: Generated by swapping the assigned locations of pairs of logical qubits involved in gates.
     • Procedure: Iteratively move to the neighboring mapping with the best metric score, using random restarts to avoid local optima.

Numerical Results (Color Code Substrate)

Simulations using the color code substrate and the hexagonal routing graph explored the compilation performance:

• Impact of Parallelism: Circuits with higher inherent parallelism benefit more from the mapping ($\Lambda^*$) optimization, especially when using sparser layouts (like the 'pair' layout) which inherently have fewer conflicts. Denser layouts ('row', 'hexagonal') might hit limitations where the heuristic metric fails to capture complex interactions if parallelism is too high.
• Impact of T Gates: Compiling CNOT+T circuits shows that performance (compiled depth $\Delta_f$) degrades with fewer magic state factories and longer factory reset times t. Using the exact compiled depth as the optimization metric for Hill Climbing yields better results than the heuristic crossing metric, especially in these challenging scenarios.
• Layout Choice: Different layouts (choices of L and A regions on the substrate) show varying performance depending on the circuit characteristics and routing density.

Conclusion and Practical Implications

The paper provides a structured approach and initial tools for compiling quantum circuits onto fault-tolerant architectures beyond the standard surface code. Key practical takeaways include:

• General Framework: The microscopic/macroscopic abstraction allows applying the compilation approach to various topological codes and hardware layouts by defining the appropriate substrate and routing constraints.
• Concrete Implementations: Detailed constructions for distance-preserving snakes and lattice surgery protocols for color codes and folded surface codes are provided, including automated generation in the accompanying open-source code (mqt-qecc on GitHub).
• Compilation Algorithms: Practical algorithms (shortest-first VDP, Hill Climbing) are presented to tackle the routing and mapping problems, considering factors like circuit parallelism and magic state availability.
• Trade-offs: The numerical results highlight trade-offs between layout density, circuit parallelism, T-gate overhead, and the effectiveness of optimization heuristics.

This work represents a step towards practical fault-tolerant compilation for alternative topological codes, enabling exploration of different hardware architectures and potentially more efficient resource utilization compared to surface-code-only approaches.