Noise-aware selection of circuit cutting strategies under hardware noise non-uniformity

Abstract: Noise in contemporary quantum hardware is highly non-uniform across qubits and couplers, giving rise to localized low-noise "islands" within otherwise noisy device topologies. As quantum workloads scale, executions are increasingly forced to traverse high-noise regions, degrading algorithmic fidelity. Circuit cutting provides a route to circumvent such regions by decomposing large circuits into smaller subcircuits, but its practicality is limited by exponential sampling overhead and the lack of systematic guidance on how cut strategies should align with heterogeneous hardware noise. In this work, we present a hardware-noise-aware circuit cutting framework that explicitly exploits the spatial non-uniformity of noise in quantum devices. Rather than proposing a new cut-finding algorithm, we formalize the problem of device-constraint selection under realistic hardware noise and show that this choice critically determines both execution overhead and effective noise. Using a unified gate- and wire-cutting formulation, we demonstrate that small, hardware-informed relaxations in the device constraint yield exponential reductions in execution overhead while preserving alignment with low-noise hardware regions. Across representative workloads, our method achieves an average reduction in the number of circuit executions ranging from 5-54x for 20-qubit circuits, and enables tractable circuit cutting for 50-qubit circuits and application-level benchmarks where conventional strategies incur prohibitive overhead. These results establish noise-aware device-constraint selection as a necessary ingredient for making circuit cutting resource-efficient and practically deployable on contemporary quantum hardware.

• The paper presents the HIC framework that selects circuit cutting strategies based on hardware noise non-uniformity to reduce execution overhead.
• It employs hardware pruning to identify low-noise components and uses a weighted layout score to optimize subcircuit placements.
• Experimental results show up to five orders of magnitude reduction in circuit executions while maintaining observable fidelity.

Noise-Aware Quantum Circuit Cutting Under Hardware Non-uniformity

Introduction

Quantum computation has advanced towards utility-scale applications, scaling up circuit workloads with increased qubit count and depth. Modern superconducting devices, demonstrated by platforms such as IBM Quantum, now feature hundreds of qubits. However, noise characteristics exhibit significant spatial non-uniformity across these devices: certain subsets of qubits and couplers maintain superior fidelity, forming localized "islands" of low noise, while others degrade quantum operation reliability. As circuit workloads span the full hardware topology, aligning circuit execution with low-noise regions becomes infeasible, and algorithmic fidelity declines.

Circuit cutting techniques decompose quantum circuits into smaller subcircuits managed separately, potentially rerouting computation around noisy regions. Sampling overhead for reconstruction of whole-circuit observables grows exponentially with the number of cuts, especially under naive equal partitioning or uninformed constraints. The paper "Noise-aware selection of circuit cutting strategies under hardware noise non-uniformity" (2604.24422) formalizes device-constraint selection as a central optimization, directing the partitioning process such that cut strategies are aligned with spatial noise heterogeneity in the hardware.

Hardware-Inspired Cutting (HIC) Framework

The proposed HIC framework addresses device-constraint selection in the context of non-uniform noise. HIC does not replace existing cut location algorithms; rather, it augments their efficacy by guiding them towards resource-efficient, noise-resilient strategies.

HIC involves three main stages:

1. Pruning the hardware coupling map based on qubit and connectivity noise profiles by removing outlier elements.
2. Identifying the connected (low-noise) components of the punctured topology as candidate subcircuit placements.
3. Parallelizing cut-finding routines across various device-constraint values, ultimately selecting the strategy that minimizes a weighted layout score $W_s$, capturing both placement quality and noise uniformity.

   Figure 1: Workflow for HIC, detailing hardware pruning, connected component enumeration, and parallelized cut strategy selection by weighted layout score minimization.

Constructing Punctured Coupling Maps and Device Constraints

The coupling map for the hardware is a graph representation, where vertices correspond to physical qubits and edges to two-qubit connections. The noise characteristics from calibration routines generate error rate distributions. The Z-score filtering eliminates outlier qubits and connectivities, yielding a punctured coupling map comprising connected components—each representing an "island" of relatively low noise.

Figure 2: Example noise profile of a 133-qubit device illustrating striking non-uniformity in the distribution of noise across both qubits and two-qubit connectivities.

Figure 3: Punctured coupling map after outlier elimination; blue elements denote retained sections corresponding to low-noise regions suitable for subcircuit placement.

The connected components after puncturing serve as natural upper bounds for subcircuit size during circuit cutting. Device constraints are systematically selected based on these component sizes, enabling subcircuits to inhabit much lower-noise regions, even as their size is maximized for hardware utilization.

Objective Function and Layout Score

The selection of the optimal cut strategy among all candidates is governed by a weighted average layout score $W_s$. This metric is defined as a weighted sum across subcircuit placements, considering both their noise characteristics and the qubit count per subcircuit. While terms capturing noise variance among subcircuits theoretically improve partitioning balance, empirical results demonstrate high correlation with the aggregate score, enabling simplification in practice.

Figure 4: Correlation statistics between norm-1 and norm-2 of the objective $W$ for random circuits, supporting the simplification to weighted average metrics.

This scoring formulation ensures the selected cut strategy minimizes exposure to hardware noise, avoids highly unbalanced partitions, and is compatible with hardware topology.

Empirical Evaluation and Numerical Results

Experimental results on both structured and random circuits (20 and 50 qubits) as well as application benchmarks demonstrate substantial efficiency gains. HIC yields exponential reductions in circuit execution overhead. A 20-qubit mirrored QAOA circuit, partitioned with HIC, required only 128 circuit executions versus 2592 for noise-agnostic equal partitioning—despite using fewer cuts and achieving comparable or improved observable accuracy.

Figure 5: Quantitative comparison for QAOA circuits illustrating orders-of-magnitude reduction in circuit executions with HIC, while not sacrificing observable fidelity.

For random Clifford circuits, HIC strategies using gate cuts provide further execution reduction and superior alignment with low-noise hardware subcomponents. Aggressive cut budget reductions using HIC do reveal the expected degradation in output quality, but the sampling overhead reductions remain significant. Importantly, for 50-qubit circuits, HIC transforms circuit cutting from infeasible (as equal partitioning would require $> 43$ million circuit executions) to tractable (requiring only hundreds of executions).

Figure 6: Comparison for a random Clifford circuit showing the impact on execution count, weighted layout score, and output quality across different cut-budget strategies.

Figure 7: Lower-depth random Clifford circuit results, emphasizing the balance between reduced execution overhead and output accuracy.

Figure 8: 50-qubit QAOA circuit case; HIC reduces the execution requirements from millions to hundreds, making circuit cutting feasible and operationally valuable.

Benchpress suite application circuits reinforce the practical relevance, as HIC regularly reduces quantum overhead (up to five orders of magnitude) with minimal impact on layout score, indicating preserved or sometimes even improved output quality.

Comparative Analysis with Existing Circuit Cutting Approaches

HIC outperforms conventional cut-finding approaches (CutQC, FragQC) by automating device-constraint selection based on hardware noise rather than relying on user intuition. HIC's classical pre-processing cost is offset by its parallelizability and the feasibility outcomes it enables. Wire-cut-only strategies fail for circuits requiring gate cuts—an explicit gap filled by HIC.

Figure 9: Circuit topology illustrating cases where wire-cut strategies cannot succeed due to long-range two-qubit gates, but HIC (with gate cuts) produces viable partitions.

Implications and Future Directions

HIC demonstrates that device-constraint selection aligned with spatial noise properties is critical for scalable quantum circuit cutting. The implications are twofold:

• Resource-efficient quantum compilation: By greatly reducing circuit execution overhead and aligning partitioned circuits with hardware noise islands, HIC makes circuit cutting practical on large noisy devices (up to 50-qubit scale).
• Strategic parallelization and scheduling: Although HIC prioritizes output quality, its compatibility with parallel execution (either intra- or inter-device) opens avenues for further latency reduction and hardware utilization optimization.

Theoretical implications include refining layout-score models, online adaptive constraint selection, and the integration with error mitigation and operator backpropagation techniques for further performance improvement. Future directions may include predictive modeling of layout score versus observable degradation, and incorporating scheduling objectives.

Conclusion

This paper establishes noise-aware device-constraint selection as a necessary optimization for practical circuit cutting. By systematically leveraging spatial noise non-uniformity (punctured coupling maps and weighted layout scores), HIC enables circuit cutting to become a deployable resource-efficient technique for contemporary noisy quantum hardware. The framework is operationally validated across circuit and application benchmarks, outperforming standard approaches and extending the applicability of circuit cutting towards near-term quantum advantage.