Multi-Plane HyperX: A Low-Latency and Cost-Effective Network for Large-Scale AI and HPC Systems

Abstract: Multi-plane architectures have become increasingly prevalent in the Fat-Tree networks of AI data centers. By leveraging multiple ports on a single network interface card (NIC) or multiple NICs within a scale-up domain, each port or NIC is allocated to an independent network plane, thereby provisioning the overall system with multiple network planes. However, no prior literature has explored the application of multi-plane technologies to direct networks such as HyperX. This paper investigates the multi-plane HyperX network and demonstrates that, compared to state-of-the-art network topologies like multi-plane Fat-Tree, Dragonfly, and Dragonfly+, the multi-plane HyperX architecture achieves a significantly smaller network diameter and superior cost-effectiveness.

• The paper introduces a Multi-Plane HyperX design that significantly reduces network diameter and per-NIC cost compared to Fat-Tree and Dragonfly alternatives.
• It employs multi-plane partitioning to leverage multi-port NICs for enhanced bandwidth utilization and improved latency in AI and HPC workloads.
• The study highlights hardware challenges in NIC and switch configurations while paving the way for scalable, cost-effective exascale network deployments.

Multi-Plane HyperX: A Low-Latency and Cost-Effective Network Architecture for Large-Scale AI and HPC

Introduction

This paper introduces the Multi-Plane HyperX (MPHX) network, extending multi-plane design principles beyond Fat-Tree topologies to direct networks, specifically HyperX. The motivation arises from the increasing deployment of multi-plane Fat-Tree architectures in large-scale AI and HPC systems, leveraging multi-port NICs and port breakout capabilities to optimize bandwidth utilization, reduce network diameter, and improve cost-performance ratios. The research systematically analyzes the implications and benefits of adopting multi-plane approaches for HyperX networks, yielding compelling reductions in network diameter and per-node cost relative to Fat-Tree, Dragonfly, and Dragonfly+ topologies.

Background and Motivation

Modern large-scale clusters frequently use NICs with multiple ports, enabling multi-plane architectures that partition physical infrastructure into independent logical planes. Industry examples like Alibaba’s HPN 7.0 and DeepSeek’s ideal multi-plane network exemplify these trends in Fat-Tree-based networks. While such architectures reduce the complexity and cost associated with traditional Fat-Tree core layers and provide fault isolation, these approaches have been largely neglected in direct networks, notably HyperX and its generalized routing and topology flexibility.

The authors identify that the synergy between port breakout on high-radix switches (e.g., 51.2 Tbps devices with up to 512 × 200 Gbps ports) and multi-port NICs presents a natural opportunity to radically reduce network diameter, minimize latency, and attain significant cost benefit by extending the multi-plane principle to HyperX, which intrinsically supports flexible multi-dimensional direct interconnection.

MPHX Architecture and Topological Analysis

MPHX extends traditional HyperX by incorporating multiple parallel planes, each constructed from a subnet of the global infrastructure, with every NIC port assigned to a separate plane. The configuration and scalability can be precisely parameterized:

• $n$: Number of NIC ports (planes)
• $B$: Aggregate NIC bandwidth, divided evenly across $n$ ports
• $k$: Maximum switch radix
• $D$: Number of HyperX dimensions
• $p$: Switch attachment points per NIC

For a $D$-dimensional HyperX network, the total number of NICs supported is:

$N = p \cdot \prod_{i=1}^D D_i$

where the balanced, maximum configuration is optimal at $p = D_1 = \ldots = D_D = \frac{nk}{D+1}$, leading to:

$N_{\text{max}} = \left(\frac{nk}{D+1}\right)^{D+1}$

The resulting topology features each plane as an independent HyperX network. In the practical context discussed, $B$0 is assumed up to 8, matching realistic hardware constraints.

Figure 1: 4-plane 1D HyperX (MPHX(4,4,4)) network. Each NIC is equipped with four ports, with each port belonging to an independent 1D HyperX network plane.

As illustrated, each NIC port forms an endpoint for an independent plane, achieving robust bandwidth partitioning and enhanced resilience.

Cost and Performance Comparison

A core claim substantiated in this work is the substantial cost reduction and latency improvement afforded by MPHX as compared to state-of-the-art alternatives. Assuming contemporary 102.4 Tbps switches configured (via breakout) from 64 × 1.6 Tbps to 512 × 200 Gbps, the paper evaluates the capital expense for constructing a 65,536-NIC system:

• A 3-tier Fat-Tree incurs high per-NIC cost (\$10,323).
• Multi-plane Fat-Tree (8 planes, 2 layers) reduces this to \$5,075 per NIC.
• Canonical Dragonfly and Dragonfly+ variants lie in the range \$B$18,500 per NIC.</li> <li>Multi-plane HyperX configurations exhibit the lowest cost, especially at higher plane counts (e.g., MPHX(8,256,256): \$3,647 per NIC).

Additionally, MPHX yields the smallest network diameters under comparable scales, directly translating to reduced communication latency.

Key quantitative finding:

The MPHX topology, at high plane counts, reduces average per-NIC cost by 28% relative to the most competitive multi-plane Fat-Tree variant, with further gains when copper connections are deployed at the network edge.

Convergence With Alternative Topologies

The paper argues that the generalization of multi-plane technology is topology-agnostic. Increasing switch radix and port breakout in Dragonfly and Dragonfly+ networks ultimately flattens these hierarchical designs, converging them toward multi-plane HyperX topologies. This effect is substantiated by a Frontier-like case study, where greater port counts obviate the need for hierarchical “global” switches, essentially morphing the network into a 2D or even 1D HyperX. Similarly, the Zettafly series exhibits the same flattening behavior when port counts are extremely high.

Implementation Challenges

Deploying MPHX raises nontrivial NIC and switch design challenges:

• NICs must intelligently distribute flows across planes (requiring native support for sophisticated load balancing and out-of-order packet management).
• Switches must support adaptive routing, given that bandwidth for minimal paths in a single plane may be insufficient under cross-plane traffic; efficient load balancing mandates non-minimal path support.

Thus, while MPHX provides architectural and economic advantages, hardware-level innovations in both NICs and switches are prerequisites for efficient, scalable deployment.

Implications and Future Directions

The practical and theoretical implications of MPHX are significant:

• For hyperscale AI and HPC clusters, MPHX minimizes network diameter, thus improving worst-case communication latency for bandwidth-centralized workloads such as distributed DNN training and graph analytics.
• Its cost structure enables denser deployments under fixed budgets, thereby enhancing FLOPS/dollar at the cluster scale.

The authors note the necessity of further work, promising comprehensive routing protocol design and experimental benchmarking (including synthetic and application-level workloads), in order to fully characterize latency, congestion, and fault resilience under MPHX. The evolution of networking hardware—particularly higher-radix switches and programmable NICs—will increasingly favor adoption of MPHX-like architectures across both research and industry.

Conclusion

Multi-Plane HyperX emerges as a technically and economically compelling alternative to current large-scale network interconnects. By integrating multi-plane partitioning with direct HyperX topology, it pushes the boundary of cost-performance and scalability for modern AI and HPC infrastructures. While implementation complexity at the NIC and switch level remains a challenge, the forecasted reductions in both per-node cost and network latency position MPHX as a key candidate for next-generation exascale systems.