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In-Situ Simultaneous Magic State Injection on Arbitrary CSS qLDPC Codes

Published 6 Apr 2026 in quant-ph | (2604.05126v1)

Abstract: Quantum low-density parity-check (qLDPC) codes can encode many logical qubits within a single code block at low physical qubit overhead, yet magic state injection into such codes remains largely underexplored. Existing state injection proposals for qLDPC codes predominantly follow an external prepare-and-transfer paradigm, in which raw magic states are prepared outside the target code block and subsequently injected via inter-code operations. We propose the first \emph{in-situ} magic state injection: a scheme in which logical magic states are directly prepared within a qLDPC memory block, only using resources required for syndrome extraction. We show that our scheme is generalizable to any CSS qLDPC code, with examples of circuit-level simulations on the $[[144,12,12]]$ Bivariate Bicycle (BB) code and the $[[225,9,4]]$ Hypergraph Product code. We focus on a regime where correlated injection errors are negligible. In the BB code, this corresponds to a configuration that simultaneously injects four logical $|Y\rangle$ states. Under a uniform depolarizing noise model with physical error rate $10{-3}$, this achieves an injection error rate of $1.62 \times 10{-3}$ per logical qubit, while the correlated-error contribution is only $2 \times 10{-5}$ per logical qubit (about $1\%$ of the injection error rate). Under a hardware-motivated asymmetric noise model where single-qubit gate errors are $10\%$ of two-qubit gate errors, the injection error rate per logical qubit falls to $ 6.7 \times 10{-4} $, below the error rate ($ 10{-3} $) of the two-qubit gates used to encode the magic states. Its simplicity allows our scheme to be applied to arbitrary CSS qLDPC codes using only the ancilla qubits native to syndrome extraction, and yield a reduction in space overhead relative to both prepare-and-transfer approaches and surface-code-based magic state injection schemes.

Summary

  • The paper introduces an in-situ protocol that simultaneously injects up to k logical magic states into arbitrary CSS qLDPC codes, drastically reducing ancilla and spatial overhead.
  • It employs stabilizer-cleaning combined with MILP-based optimization and noise-aware postselection to achieve low logical error rates, outperforming conventional two-qubit gate benchmarks.
  • Numerical simulations on BB and HGP codes demonstrate trade-offs in discard rates and injection fidelity, establishing a scalable approach for resource state preparation in high-rate quantum architectures.

In-Situ Simultaneous Magic State Injection for Arbitrary CSS qLDPC Codes

Introduction

This work addresses the critical challenge of high-fidelity, low-overhead magic state injection (MSI) in quantum low-density parity-check (qLDPC) codes, particularly focusing on arbitrary Calderbank-Shor-Steane (CSS) qLDPC codes. While qLDPC codes are recognized for their asymptotic encoding rates and spatial compactness, their practical utilization for non-Clifford resource state preparation—specifically MSI—has remained largely unexamined beyond prepare-and-transfer paradigms. The authors introduce and analyze, for the first time, a fully in-situ MSI primitive for generic CSS qLDPC codes, drastically reducing ancilla and space overheads and advancing raw resource generation directly compatible with the architecture's error-correction infrastructure.

Background and Motivation

The Eastin-Knill theorem precludes the existence of universal transversal logical gate sets in quantum codes, positioning magic state distillation pipelines as the operational cornerstone for non-Clifford gate implementation. Surface codes and color codes have well-characterized MSI techniques, but these are not directly transferable to high-rate qLDPC codes due to their code structure and logical operator support overlaps. Prior efforts for MSI in qLDPC codes have depended on resource-intensive prepare-and-transfer methods or code switching to specialized subcodes, neither of which exploit the inherent multicore encoding of qLDPC memory blocks nor realize truly native resource state injection.

Principal Scheme and Generalization

The core contribution is a general protocol for simultaneously injecting up to kk logical magic states into an arbitrary [[n,k,d]][[n, k, d]] CSS qLDPC code block. The scheme employs only those ancilla qubits essential for syndrome extraction, repurposing the code’s intrinsic measurement resources without requiring auxiliary logic blocks. The construction leverages stabilizer-cleaning to select logical Pauli representatives with near-disjoint supports, thereby enabling logical state initialization through local operations and Clifford circuits. The general method is agnostic to both the code’s low-density structure and physical connectivity, making it widely applicable across CSS code families, including modern high-rate constructions such as the Bivariate Bicycle (BB) and Hypergraph Product (HGP) codes.

Noise-Aware Injection Optimization

While the generic method achieves functional MSI, correlated logical errors and first-round undetected faults can yield unacceptably high logical error rates. The paper introduces a refined, noise-aware protocol that strategically employs postselection on deterministic stabilizer outcomes (“fixed stabilizers”) during the first round of syndrome extraction. This postselection is enabled by a preparation pattern combining direct magic state initialization on injection sites and Bell state preparation on logical support overlaps, maximizing the detection coverage for single-qubit errors. An MILP-based optimization determines the maximal set of simultaneously injectable logical qubits that satisfies both stabilizer-detection and code-specific commutation constraints. This regime suppresses correlated logical faults to levels compatible with downstream magic state distillation (less than 1% of the single-logical error rate in the optimized BB code instance), and realizes per-logical-qubit injection error rates well below the two-qubit gate error rate in hardware-relevant asymmetric noise models.

Numerical Results and Comparative Analysis

Circuit-level simulations benchmark the method on the [[144,12,12]][[144,12,12]] BB code and the [[225,9,4]][[225,9,4]] HGP code, under both uniform depolarizing and hardware-asymmetric noise models. Notable findings include:

  • Simultaneous injection of 4 logical Y|Y\rangle states in the BB code achieves a logical injection error rate of 1.62×1031.62 \times 10^{-3} per logical qubit (discard rate 93%\approx 93\%) under p=103p=10^{-3} physical error, with the correlated error contribution 2×105\sim 2 \times 10^{-5}.
  • Under single-qubit gate errors at 10%10\% of two-qubit gate errors, per-logical-qubit injection error rate reduces to [[n,k,d]][[n, k, d]]0, outperforming the base two-qubit gate fidelity.
  • Comparable injection in the HGP code yields higher error rates and discard rates, underscoring the importance of tailored code-specific optimization of logical operators and syndrome extraction circuits.
  • Compared to leading surface code injection schemes ("hook injection"), BB code MSI offers a significant reduction in physical qubit footprint (288 vs. 968 for 4 logicals at similar distance), though at a cost in higher discard rates and marginally elevated logical error rates.

These metrics situate the scheme as highly relevant for low-footprint, multicore logic architectures and NISQ-scale demonstrations, although further advancements are required to challenge the lowest-overhead surface code MSI protocols in terms of throughput and unamortized logical fidelity.

Theoretical Insights and Postselection Behavior

Analytical modeling (via detector error models) and empirical rates demonstrate that first-round stabilizer postselection efficiently captures dominant error sources, with the discard rate governed by the interplay between fixed-stabilizer and round-parity detectors. MILP optimization prioritizing support coverage over raw stabilizer count yields superior fault detection. The injection protocol’s correlated-error component remains minimal for optimal configurations with [[n,k,d]][[n, k, d]]1, validating the assumptions underpinning downstream distillation protocols.

Practical Implications and Future Directions

The proposed MSI primitive enables genuinely qLDPC-native resource state preparation, drastically reducing qubit overhead and integration complexity in high-rate quantum memory architectures. This compactness is critical for implementations where qubit resources are severely constrained, and for scalable logical block operation in modular and distributed quantum systems.

Notwithstanding these advances, several open questions persist:

  • Scalability: Increasing the number of simultaneously injectable logical qubits without incurring excess correlated errors or unsustainable discard rates remains an open combinatorial and circuit-design problem.
  • Further code optimization: Logical operator selection and syndrome extraction scheduling tailored specifically for the injection protocol can materially reduce both logical error and overhead.
  • Hardware adaptation: Customization of the injection protocol for specific device topologies and native gate sets, including mitigating the cost of Bell state preparation in non-fully connected architectures.
  • Throughput and pipeline integration: Merging the MSI schedule with qLDPC-native cultivation and distillation schemes can yield end-to-end resource state preparation protocols with better trade-offs between footprint, logical error rate, and time-to-magic-state.

Conclusion

This work defines a new standard for magic state injection in high-rate CSS qLDPC codes, presenting a universal, in-situ, and scalable protocol with strong space overhead reductions, compelling logical error rates, and low correlated error contributions. The approach establishes a technical foundation for fully qLDPC-native non-Clifford resource state pipelines and prompts further research into code- and hardware-aware optimization. As logical qubit counts scale in future quantum processors, such methods are expected to become essential elements of practical fault-tolerant computation.

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