MINISA: Minimal Instruction Set Architecture for Next-gen Reconfigurable Inference Accelerator

Abstract: Modern reconfigurable AI accelerators rely on rich mapping and data-layout flexibility to sustain high utilization across matrix multiplication, convolution, and emerging applications beyond AI. However, exposing this flexibility through fine-grained micro-control results in prohibitive control overhead of fetching configuration bits from off-chip memory. This paper presents MINISA, a minimal instruction set that programs a reconfigurable accelerator at the granularity of Virtual Neurons (VNs), the coarsest control granularity that retains flexibility of hardware and the finest granularity that avoids unnecessary control costs. First, we introduce FEATHER+, a modest refinement of FEATHER, that eliminates redundant on-chip replication needed for runtime dataflow/layout co-switching and supports dynamic cases where input and weight data are unavailable before execution for offline layout manipulation. MINISA then abstracts control of FEATHER+ into three layout-setting instructions for input, weight, and output VNs and a single mapping instruction for setting dataflow. This reduces the control and instruction footprint while preserving the legal mapping and layout space supported by the FEATHER+. Our results show that MINISA reduces geometric mean off-chip instruction traffic by factors ranging from 35x to (4x10^5)x under various sizes under 50 GEMM workloads spanning AI (GPT-oss), FHE, and ZKP. This eliminates instruction-fetch stalls that consume 96.9% of micro-instruction cycles, yielding up to 31.6x end-to-end speedup for 16x256 FEATHER+. Our code: https://github.com/maeri-project/FEATHER/tree/main/minisa.

• The paper presents the MINISA architecture, a minimal ISA leveraging Virtual Neuron abstraction to drastically reduce control overhead.
• It introduces eight core instructions and a two-stage mapping-layout pipeline that compress instruction traffic and improve throughput.
• Empirical results on FEATHER+ reveal up to 31.6× speedup and enhanced efficiency compared to contemporary GPU and TPU accelerators.

Minimal Instruction Set Architecture for Next-gen Reconfigurable Inference Accelerator (MINISA)

Introduction

The proliferation of highly diverse AI inference workloads—now spanning not only classical deep learning but also emerging domains such as Fully Homomorphic Encryption (FHE) and Zero-Knowledge Proofs (ZKP)—has accentuated the demands placed on reconfigurable AI accelerators. Acceptable throughput and utilization for such operators requires flexible mapping and data layout schemes. However, exposing this flexibility through finely-detailed micro-control incurs severe control overhead, saturating instruction fetch channels and on-chip storage as array sizes scale. The presented work addresses this bottleneck by proposing MINISA, a minimal instruction set architecture grounded in the concept of the Virtual Neuron (VN), and demonstrates its deployment on the FEATHER+ reconfigurable accelerator (2603.20623).

Architectural Abstractions and Innovations

Virtual Neuron (VN) Granularity

MINISA exploits the observation that the finest hardware atomic unit in FEATHER+ is an AH-element dot product within a Processing Element (PE). Defining the VN as this dot-product atom, MINISA elevates the abstraction point to VN-level operations. This granularity captures all hardware-supported mapping and layout flexibility, yet strips away unnecessary cycle-level micro-configuration. Operand-specific VNs (IVN, WVN, PVN, OVN) are mapped to input, weight, partial-sum, and output tensor fragments, allowing every mapping and layout operation to be specified in terms of VNs rather than individual elements.

FEATHER+ Microarchitecture Enhancements

FEATHER+ refines FEATHER by:

• Incorporating all-to-all crossbar-based distribution networks from buffers to compute arrays, eliminating data duplication and supporting runtime operand arrival.
• Simplifying buffer architectures to single-bank designs, and incorporating links from the output buffer to stationary buffers, supporting flexible input/output tensor reuse.
• Removing the stringent requirement for pre-known and pre-shuffled operands, a critical enabler for dynamic workloads typical in LLM and cryptography contexts.

These refinements preserve high compute utilization and mapping expressivity without incurring the configuration overhead that plagued previous designs.

Instruction Set Design

Instruction Types and Compression

MINISA comprises only eight core instructions:

• SetIVNLayout, SetWVNLayout, SetOVNLayout: Specify the layouts of input, weight, and output VNs in on-chip buffers, using compressed descriptors for permutation and partitioning order.
• ExecuteMapping: Configures compute tile mappings at VN granularity and triggers execution.
• ExecuteStreaming: Manages streaming dataflow and supports dynamic dataflow switching (IO-S/WO-S).
• Load, Write, Activation: Manage data movement and post-processing within the buffers.

Critically, all mapping and layout permutations are encoded in a compact manner, with bitwidths determined by architectural dimensions rather than the scale of the workload itself.

Elimination of Control Overhead

By programming at VN granularity, MINISA reduces the configuration trace size by up to a geometric mean of $2 \times 10^4$–$4 \times 10^5$× on large arrays, and compresses instruction-to-data byte ratios to less than 0.1%. For a representative FEATHER+ array of $16 \times 256$ PEs, MINISA removes the instruction-fetch stalls that, in micro-instruction baselines, consumed up to 97% of cycles.

Compilation and Execution Pipeline

The mapping and layout co-search pipeline (FEATHER+ Mapper) employs a two-stage approach:

• Mapping-first: Candidate mappings are enumerated based on tile size, VN group formation, and column duplication factors, compressing the combinatorial search space.
• Layout-selection: Given a fixed mapping, buffer layouts are selected to avoid conflicts and capacity overruns.

The pipeline deterministically translates the resulting mapping-layout pair to a MINISA instruction trace, which is then suitable for FEATHER+ hardware as well as for rapid cycle-accurate simulation.

Numerical Results and Empirical Claims

Instruction Traffic and Speedup

MINISA achieves geometric mean reductions in off-chip instruction traffic of 35× to $4 \times 10^5$× across 50 GEMM workloads encompassing AI (GPT-oss), FHE, and ZKP. Instruction-fetch stalls, which accounted for up to 96.9% of cycles in large arrays under FEATHER, are eliminated, yielding up to 31.6× end-to-end speedup on a $16 \times 256$ PE FEATHER+ instance.

Comparison with Contemporary Accelerators

FEATHER+, orchestrated via MINISA, delivers up to 23.7× (vs. RTX5090 GPU) and 7.8× (vs. TPUv6e) geometric mean speedup when processing the full shape and workload spectrum. The system retains high compute utilization even under heavily irregular GEMM shapes (e.g., those typical for FHE and ZKP), where fixed-granularity tensor-core-based approaches achieve as little as 3% utilization.

Resource Efficiency and Scalability

Area overhead induced by FEATHER+'s new distribution networks remains modest (≤ 7%). Scaling in array width delivers nearly linear improvements in throughput, with interconnect complexity scaling sub-quadratically ($O(A_W \log A_W)$ for BIRRD, $O(A_W^2)$ for distribution), whereas scaling array height increases both arithmetic intensity and required buffer capacity quadratically. The architecture scales favorably both for high-throughput regular matrix operators and for irregular cryptographic workloads.

Theoretical and Practical Implications

MINISA's chief innovation is the decoupling of mapping/layout flexibility from the high implementation cost of fine-grained control. By raising the programming abstraction to the VN—which matches the hardware's smallest dot-product atom—the design achieves a strict lower bound on control overhead for a given level of reconfigurability. This constraint is both a practical, compiler-mappable interface and a theoretical optimality result in control granularity.

Practically, this enables reconfigurable accelerators not only to close the utilization gap versus rigid architectures (TPUs, GPUs), but to do so for incomposable or irregular matrix shapes pervasive in new AI-adjacent domains. As emerging AI applications continue to diversify, especially into cryptographic primitives, algebraically structured machine learning, and generalized GEMM/convolution flows, MINISA’s programming model is likely to scale without pathological blow-up in control bandwidth.

Future Directions

Potential future work includes extending the MINISA paradigm to support:

• Irregular sparsity and structured pruning at the VN granularity.
• Online re-mapping strategies reacting to dynamic workload characteristics.
• Deeper integration into multi-accelerator systems, quantifying benefits in distributed reconfigurable computing scenarios.
• Extensions for variable-precision arithmetic or multi-modal tensor operators.

Additionally, there is scope to generalize the VN abstraction to other classes of spatial accelerators, or to hybrid architectures (CPU-accelerator, CPU-FPGA systems), offering a blueprint for low-overhead programmable flexibility.

Conclusion

MINISA, leveraging the Virtual Neuron abstraction, provides a concise, expressive, and scalable ISA for reconfigurable inference accelerators. It addresses a critical scalability bottleneck in existing systems by reducing instruction trace sizes by several orders of magnitude and eliminating instruction-fetch bottlenecks. When evaluated across extensively diverse AI and cryptographic workloads, MINISA on FEATHER+ consistently sustains high utilization, matching or surpassing mainstream AI accelerators, and significantly lowers both programming complexity and hardware control costs. This positions MINISA as a robust architectural and compiler interface for next-generation, domain-flexible inference acceleration (2603.20623).