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Limits to the Energy Efficiency of CMOS Microprocessors (2312.08595v1)

Published 14 Dec 2023 in cs.ET

Abstract: CMOS microprocessors have achieved massive energy efficiency gains but may reach limits soon. This paper presents an approach to estimating the limits on the maximum floating point operations per Joule (FLOP/J) for CMOS microprocessors. We analyze the three primary sources of energy dissipation: transistor switching, interconnect capacitances and leakage power. Using first-principles calculations of minimum energy costs based on Landauer's principle, prior estimates of relevant parameters, and empirical data on hardware, we derive the energy cost per FLOP for each component. Combining these yields a geometric mean estimate of 4.7e15 FP4/J for the maximum CMOS energy efficiency, roughly two hundred-fold more efficient than current microprocessors.

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References (65)
  1. “Implications of Historical Trends in the Electrical Efficiency of Computing” In IEEE Annals of the History of Computing 33, 2011, pp. 46–54
  2. “Moore’s law might be slowing down, but not energy efficiency” In IEEE Spectrum, 2015 URL: https://spectrum.ieee.org/moores-law-might-be-slowing-down-but-not-energy-efficiency
  3. Marius Hobbhahn, Lennart Heim and Gökçe Aydos “Trends in Machine Learning Hardware (Forthcoming)”, 2023
  4. IEEE “International Roadmap for Devices and Systems 2022 Edition – More Moore”, 2022 URL: https://irds.ieee.org/images/files/pdf/2022/2022IRDS_MM.pdf
  5. “Energy efficiency limits of logic and memory” In 2016 IEEE International Conference on Rebooting Computing (ICRC), 2016, pp. 1–8
  6. Michael P. Frank “Approaching the physical limits of computing” In 35th International Symposium on Multiple-Valued Logic (ISMVL’05), 2005, pp. 168–185
  7. David A.B. Miller “Attojoule Optoelectronics for Low-Energy Information Processing and Communications” In Journal of Lightwave Technology 35, 2016, pp. 346–396
  8. Rolf Landauer “Irreversibility and heat generation in the computing process” In IBM J. Res. Dev. 5, 1961, pp. 183–191
  9. Abdoul Rjoub, Mamoun Mistarihi and Nedal Al Taradeh “Accurate leakage current models for MOSFET nanoscale devices” In International Journal of Electrical and Computer Engineering (IJECE), 2020
  10. “Power consumption analysis in static CMOS gates” In 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 2013, pp. 1–6
  11. “Scalable energy-efficient magnetoelectric spin–orbit logic” In Nature 565, 2018, pp. 35–42
  12. Dmitri E. Nikonov and Ian A. Young “Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits” In IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 1, 2015, pp. 3–11
  13. “Optical Transformers” In ArXiv abs/2302.10360, 2023
  14. Mark Horowitz “1.1 Computing’s energy problem (and what we can do about it)” In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, pp. 10–14
  15. “GPUs and the Future of Parallel Computing” In IEEE Micro 31, 2011, pp. 7–17
  16. Franco Stellari, Alberto Tosi and Peilin Song “Switching Time Extraction of CMOS Gates using Time-Resolved Emission (TRE)” In 2006 IEEE International Reliability Physics Symposium Proceedings, 2006, pp. 566–573
  17. “Power Consumption in CMOS Circuits” In Electromagnetic Field in Advancing Science and Technology Rijeka: IntechOpen, 2022 DOI: 10.5772/intechopen.105717
  18. Juan C. Ranuárez, M.Jamal Deen and Chih-Hung Chen “A review of gate tunneling current in MOS devices” In Microelectron. Reliab. 46, 2006, pp. 1939–1956
  19. Thomas Vogelsang “Understanding the Energy Consumption of Dynamic Random Access Memories” In 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010, pp. 363–374
  20. “Efficient Processing of Deep Neural Networks: A Tutorial and Survey” In Proceedings of the IEEE 105, 2017, pp. 2295–2329
  21. “Interconnect-power dissipation in a microprocessor” In International Workshop on System-Level Interconnect Prediction, 2004
  22. Konstantin Moiseev, Avinoam Kolodny and Shmuel Wimer “An Overview of the VLSI Interconnect Problem”, 2015
  23. Vinod K. Khanna “Short-Channel Effects in MOSFETs”, 2016
  24. “NVIDIA Hopper Architecture In-Depth”, 2022 URL: https://developer.nvidia.com/blog/nvidia-hopper-architecture-in-depth/
  25. Scott E. Thompson “MOS Scaling: Transistor Challenges for the 21st Century”, 1998
  26. Venkata Ramakrishna Nandyala and Kamala Kanta Mahapatra “A circuit technique for leakage power reduction in CMOS VLSI circuits” In 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), 2016, pp. 1–5
  27. “Leakage Current: Moore’s Law Meets Static Power” In Computer 36, 2003, pp. 68–75
  28. “DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning” In Proceedings of the 19th international conference on Architectural support for programming languages and operating systems, 2014
  29. “Deep Learning with Limited Numerical Precision” In International Conference on Machine Learning, 2015
  30. Ganesh Venkatesh, Eriko Nurvitadhi and Debbie Marr “Accelerating Deep Convolutional Networks using low-precision and sparsity” In 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2016, pp. 2861–2865
  31. “Ultra-Low Precision 4-bit Training of Deep Neural Networks” In Neural Information Processing Systems, 2020
  32. “A memory frontier for complex synapses” In NIPS, 2013
  33. Anders Sandberg, Nick Bostrom and James Martin “Whole Brain Emulation”, 2008
  34. “Nanoconnectomic upper bound on the variability of synaptic plasticity” In eLife 4, 2015
  35. Joseph Carlsmith “How Much Computational Power Does It Take to Match the Human Brain?”, 2020 URL: https://www.openphilanthropy.org/research/how-much-computational-power-does-it-take-to-match-the-human-brain/
  36. Victor V. Zhirnov, Ralph K. Cavin and Luca Gammaitoni “Minimum Energy of Computing, Fundamental Considerations”, 2014 URL: https://api.semanticscholar.org/CorpusID:30075410
  37. V. Jayaprakasan, S. Vijayakumar and V.S.Kanchana Bhaaskaran “Evaluation of the Conventional vs. Ancient Computation Methodology for Energy Efficient Arithmetic Architecture” In 2011 International Conference on Process Automation, Control and Computing, 2011, pp. 1–4
  38. Shashank V M “Why would an AND gate need six transistors?” URL:https://electronics.stackexchange.com/q/533539 (version: 2021-06-13), Electrical Engineering Stack Exchange URL: https://electronics.stackexchange.com/q/533539
  39. Elad Alon, Tsu-Jae King Liu and Kelin J. Kuhn “Energy efficiency limits of digital circuits based on CMOS transistors”, 2015
  40. Nvidia “NVIDIA H100 Tensor Core GPU Architecture”, 2023 URL: https://resources.nvidia.com/en-us-tensor-core
  41. David A.B. Miller “Device Requirements for Optical Interconnects to Silicon Chips” In Proceedings of the IEEE 97, 2009, pp. 1166–1185
  42. Krishnendu Chakrabarty “ECE 261: CMOS VLSI Design Methodologies - Interconnects”, 2011 URL: http://people.ee.duke.edu/~krish/teaching/Lectures/AdvancedTopicsInterconnect.pdf
  43. Karim Abbas “Wires and Clocks”, 2020 URL: https://api.semanticscholar.org/CorpusID:213610507
  44. “Low-k dielectric materials” In Materials Today 7, 2004, pp. 34–39
  45. “Proposal for a Negative Capacitance Topological Quantum Field-Effect Transistor” In 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 38.2.1–38.2.4
  46. Suman Datta, Wriddhi Chakraborty and Marko Radosavljevic “Toward attojoule switching energy in logic transistors” In Science 378, 2022, pp. 733–740
  47. Michelle Yvonne Simmons “A single atom transistor” In 2012 IEEE Silicon Nanoelectronics Workshop (SNW), 2012, pp. 1–1
  48. “CODATA Recommended Values of the Fundamental Physical Constants: 2018.” In Journal of physical and chemical reference data 93 2, 2021
  49. “The electronic structure at the atomic scale of ultrathin gate oxides” In Nature 399, 1999, pp. 758–761
  50. Waldemar Nawrocki “Physical limits for scaling of integrated circuits” In Journal of Physics: Conference Series 248, 2010, pp. 012059
  51. David Schor “TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO”, 2019 URL: https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/
  52. IEEE “International Roadmap for Devices and Systems 2022 Edition – Executive Summary”, 2022 URL: https://irds.ieee.org/images/files/pdf/2022/2022IRDS_ES.pdf
  53. James D. Meindl and Jeffrey A. Davis “The fundamental limit on binary switching energy for terascale integration (TSI)” In IEEE Journal of Solid-State Circuits 35, 2000, pp. 1515–1516
  54. Robert M. Swanson and James D. Meindl “Ion-implanted complementary MOS transistors in low-voltage circuits”, 1972
  55. “The limit of dynamic voltage scaling and insomniac dynamic voltage scaling” In IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, 2005, pp. 1239–1252
  56. “Theoretical and practical limits of dynamic voltage scaling” In Proceedings. 41st Design Automation Conference, 2004., 2004, pp. 868–873
  57. Kamal Y. Kamal “The Silicon Age: Trends in Semiconductor Devices Industry” In Journal of Engineering Science and Technology Review, 2022
  58. Shekhar Verma and Suman Lata Tripathi “Process variation and analysis of FinFET for low-power applications” In IOP Conference Series: Materials Science and Engineering 872, 2020
  59. “Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications” In IEEE Access 7, 2019, pp. 17256–17262
  60. “Sub 50-nm FinFET: PMOS” In International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999, pp. 67–70
  61. Doug Eadline “Nvidia H100: Are 550,000 GPUs Enough for This Year?” In HPCwire, 2023 URL: https://www.hpcwire.com/2023/08/17/nvidia-h100-are-550000-gpus-enough-for-this-year/
  62. Energy Information Administration “Average Price of Electricity to Ultimate Customers by End-Use Sector” Energy Information Administration, 2023 URL: https://web.archive.org/web/20231117125354/https://www.eia.gov/electricity/monthly/epm_table_grapher.php?t=epmt_5_6_a
  63. “Reversible Computing with Fast, Fully Static, Fully Adiabatic CMOS” In 2020 International Conference on Rebooting Computing (ICRC), 2020, pp. 1–8 URL: https://api.semanticscholar.org/CorpusID:221397093
  64. International Organization Standardization “ISO/TS 80004-1:2015 Nanotechnologies — Vocabulary — Part 1: Core terms”, 2015 URL: https://www.iso.org/standard/68058.html
  65. Witold P. Maszara and M.-R. Lin “FinFETs — Technology and circuit design challenges” In 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013, pp. 3–8
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