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Self-Learning Tuning for Post-Silicon Validation (2111.08995v3)
Published 17 Nov 2021 in cs.LG and cs.AI
Abstract: Increasing complexity of modern chips makes design validation more difficult. Existing approaches are not able anymore to cope with the complexity of tasks such as robust performance tuning in post-silicon validation. Therefore, we propose a novel approach based on learn-to-optimize and reinforcement learning in order to solve complex and mixed-type tuning tasks in a efficient and robust way.