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SVE-enabling Lattice QCD Codes (1901.07294v1)
Published 22 Jan 2019 in cs.DC and hep-lat
Abstract: Optimization of applications for supercomputers of the highest performance class requires parallelization at multiple levels using different techniques. In this contribution we focus on parallelization of particle physics simulations through vector instructions. With the advent of the Scalable Vector Extension (SVE) ISA, future ARM-based processors are expected to provide a significant level of parallelism at this level.
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