Worst-case transient excitation determination for heterogeneous-integration power delivery
Determine the worst-case time-varying current patterns that produce the largest voltage drop or worst thermal profile across package-to-chip power-delivery-network interfaces in 3D heterogeneous-integration systems, particularly for highly dynamic AI workloads.
References
An open problem over many decades has been that of determining the worst-case current patterns that result in the largest voltage drop, or the worst thermal profile.
Scaling such methods to high power levels and fast response times remains an open problem.
Several open problems remain, e.g., (a)~regulator placement under transient loads; (b)~simultaneous optimization of the PDN topology, decap insertion, and regulator placement; (c)~regulator placement that is conscious of the regulation capabilities on individual chiplets; (d)~thermally aware placement that keeps regulators away from the hot spots; (e)~ML-assisted strategies for solving all of these problems.