Jenga impact and WCET analysis on complex real-time architectures
Evaluate the impact of the Jenga attack and extend the PRAC-aware WCET analysis to real-time platforms incorporating operating systems, cache hierarchies, and multi-core processor and memory architectures, including the effects of contention, cache hits, pipeline overlap, and out-of-order execution.
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Although we expect the Jenga attack to remain applicable on more complex systems, evaluating its impact under these architectures is an important direction for future work. Our current WCET analysis focuses on a simple architecture and does not account for the effects introduced by more complex processor and memory hierarchies. For instance, cache hits may mask part of the RFM-induced latency overhead, while pipeline overlap and out-of-order execution may reduce the observable impact of DRAM stalls. Extending the analysis to account for these mechanisms would enable tighter and less pessimistic WCET bounds.
In this class of systems, however, the problem of inter-core temporal interference due to the extensive sharing of hardware resources in the memory hierarchy remains an open challenge.