Extending 3D FPGA placement to support more than two layers

Extend 3D FPGA placement to support fabrics with more than two layers by addressing reachability constraints that occur in deeper stacks when only certain logic block pins provide vertical connections, ensuring that nets between non-adjacent layers (e.g., from layer 1 to layer 3) remain routable through appropriate modifications to the routing architecture and/or the placement formulation.

Background

The paper focuses on 3D FPGA architectures with two layers, noting that this setting aligns with near-term integration scenarios and captures key placement challenges. The proposed placement flow integrates partitioning-based initialization, refined 3D delay modeling, adaptive cost scheduling, and an expanded 3D move set within the VTR framework.

The authors highlight that extending the flow to deeper stacks is non-trivial due to fundamental reachability constraints. When only specific pins support vertical connections, nets between non-adjacent layers may be unroutable without intermediate resources, implying that both the routing architecture and placement formulation may require changes. This establishes the need for a generalized multi-layer (>2) 3D placement solution that handles such constraints.

References

Extending the flow to more than two layers is non-trivial and is left for future work. Unlike the two-layer case, deeper stacks introduce fundamental reachability constraints. For example, if only certain pins support vertical connections, nets between non-adjacent layers (e.g., layer 1 to layer 3) may be unroutable without intermediate resources. Addressing this would require changes to either or both of the routing architecture and placement formulation, which are beyond the scope of this work.

— Escaping Flatland: A Placement Flow for Enabling 3D FPGAs  (2604.01078 - Hao et al., 1 Apr 2026) in Footnote in Section 3 (3D FPGA Architectures) following the paragraph restricting evaluation to two-layer fabrics