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Exact plunger gate voltage range used for Device A1 parity readout

Ascertain the exact plunger-gate voltage range employed during the parity readout in Device A measurement 1 (Device A1) reported by Microsoft Quantum, Nature 638, 651–655 (2025), explicitly accounting for hysteresis and cross-capacitance between gates to resolve the ambiguity in the experimental parameter mapping.

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Background

The plunger gate setting is critical for mapping the readout region to the TGP phase diagram and conductance cuts. The comment notes that due to hysteresis and cross-capacitance effects, the exact plunger voltage range used during the reported readout is not clearly specified, complicating interpretation and reproducibility.

Clarifying the precise gate voltage range would help reconcile discrepancies between TGP outcomes and conductance data and enable accurate replication of the measurement conditions.

References

The horizontal dashed line is the plunger cut shown in Fig.~\ref{A1_con}, but it should be noted that the exact corresponding plunger voltage range used for this `readout' is unclear due to "hysteresis" and "cross capacitance".

— Comment on "Interferometric single-shot parity measurement in InAs-Al hybrid devices", Microsoft Quantum, Nature 638, 651-655 (2025) (2503.08944 - Legg, 11 Mar 2025) in Figure 1 caption (Readout region in Device A1 reported as both gapped and gapless depending on magnetic field range)