Empirical validation of YANA’s event-driven power savings on FPGA

Determine the power savings achieved by the event-driven processing pipeline of the YANA FPGA-based spiking neural network accelerator on field-programmable gate array hardware through empirical measurement, to validate power-efficiency claims associated with the Neuromorphic Advantage.

Background

YANA is designed around event-driven processing to exploit temporal and spatial sparsity in spiking neural networks, a key pathway to achieving energy efficiency in neuromorphic computing. While the architecture and experiments demonstrate latency reductions, the work does not provide measurements of power savings on FPGA hardware.

The authors explicitly note that the actual power savings from YANA’s event-driven approach have not yet been empirically demonstrated and outline future work to conduct detailed power characterization, including load-dependent strategies such as clock gating and SRAM sleep modes. Establishing these measurements is critical for substantiating the Neuromorphic Advantage in practical deployments.

References

While event-driven processing is a fundamental design principle of YANA, the actual power savings achieved through this approach on FPGA hardware have yet to be empirically demonstrated.

— YANA: Bridging the Neuromorphic Simulation-to-Hardware Gap  (2604.03432 - Pachideh et al., 3 Apr 2026) in Section 5: Discussion and Future Work (Event-Driven Power Efficiency Validation)