Demonstrate tinyRSNN performance on physical neuromorphic hardware

Demonstrate and quantify the decoding accuracy and energy-efficiency of the tinyRSNN architecture when deployed on physical neuromorphic hardware suitable for fully implanted brain–machine interfaces, verifying that its performance gains persist under real hardware constraints.

Background

tinyRSNN is designed for resource-constrained, fully implanted BMI applications, achieving high decoding performance with low memory, sparse activity, and reduced synaptic operations. The authors estimate energy benefits but have not validated the model on real hardware.

They explicitly state that performance on physical neuromorphic processors has not yet been demonstrated, and they intend to implement the model in future work.

References

Although tinyRSNN constitutes a parsimonious model that should in principle be suitable for a hardware implementation, we have not formally shown its performance gains on physical hardware.

— Decoding finger velocity from cortical spike trains with recurrent spiking neural networks (2409.01762 - Liu et al., 3 Sep 2024) in Section: Discussion and Conclusion