Papers
Topics
Authors
Recent
Gemini 2.5 Flash
Gemini 2.5 Flash
149 tokens/sec
GPT-4o
9 tokens/sec
Gemini 2.5 Pro Pro
47 tokens/sec
o3 Pro
4 tokens/sec
GPT-4.1 Pro
38 tokens/sec
DeepSeek R1 via Azure Pro
28 tokens/sec
2000 character limit reached

A Novel Reconfigurable Vector-Processed Interleaving Algorithm for a DVB-RCS2 Turbo Encoder (2308.14128v2)

Published 27 Aug 2023 in cs.IT, cs.AR, and math.IT

Abstract: Turbo-Codes (TC) are a family of convolutional codes enabling Forward-Error-Correction (FEC) while approaching the theoretical limit of channel capacity predicted by Shannons theorem. One of the bottlenecks of a Turbo Encoder (TE) lies in the non-uniform interleaving stage. Interleaving algorithms require stalling the input vector bits before the bit rearrangement causing a delay in the overall process. This paper presents performance enhancement via a parallel algorithm for the interleaving stage of a Turbo Encoder application compliant with the DVB-RCS2 standard. The algorithm efficiently implements the interleaving operation while utilizing attributes of a given DSP. We will discuss and compare a serial model for the TE, with the presented parallel processed algorithm. Results showed a speed-up factor of up to 3.4 Total-Cycles, 4.8 Write and 7.3 Read.

Summary

We haven't generated a summary for this paper yet.