HiAER-Spike: Event-Driven Neuromorphic Computing at Massive Scale
This presentation explores HiAER-Spike, a hardware-software co-design platform that uses reconfigurable FPGA technology and hierarchical spike routing to execute spiking neural networks with up to 160 million neurons and 40 billion synapses. We examine how the system leverages sparse, event-driven computation, pointer-based memory organization, and hardware-aware network partitioning to achieve low-latency, energy-efficient neuromorphic processing that is publicly accessible through the Neuroscience Gateway.Script
Most artificial intelligence burns energy computing things that never happen. The brain takes the opposite approach: it processes events only when and where they occur, using discrete spikes that travel along sparse pathways. HiAER-Spike brings this event-driven strategy to large-scale neuromorphic hardware, targeting networks with 160 million neurons and 40 billion synapses.
The key challenge is that conventional neural network storage assumes dense connectivity, allocating memory for every possible connection. Real spiking networks are radically sparse: most neurons never connect to most other neurons, and at any moment only a tiny fraction generate spikes. The researchers use pointer-based adjacency lists stored in high-bandwidth memory, where each neuron or input axon points to a compact list of its actual outgoing synapses, avoiding the cost of representing connections that do not exist.
Routing those spikes across millions of neurons distributed over dozens of FPGA boards requires a hierarchical strategy the authors call HiAER, for Hierarchical Address-Event Routing. When a neuron spikes, its address travels up through network-on-chip links, FireFly interconnects, and Ethernet, reaching exactly the distant cores that need to know about it. This multi-level event-passing architecture mirrors the brain's combination of dense local processing and sparse long-range communication.
Each FPGA uses a hybrid memory strategy to balance capacity, bandwidth, and energy. Synaptic connectivity lives in 8 gigabytes of high-bandwidth memory, accessed when a spike occurs. Frequently used spike and axon metadata sit in faster on-chip block RAM, while neuron membrane potentials reside in the fastest ultra-RAM closest to the processing cores. The authors demonstrated a 103,680-neuron gesture-recognition network running on a single core with 311 microsecond latency per frame and an estimated energy cost of just 130 microjoules.
That demonstration used less than one tenth of one percent of the planned system capacity. The full platform is designed to scale across 40 FPGA boards distributed over multiple servers, but only one core on one board is operational in the reported results. The path from a working proof-of-concept to 160 million neurons and 40 billion synapses remains a significant engineering challenge, not yet a demonstrated reality.
What makes HiAER-Spike particularly valuable is that researchers can access it remotely through a Python interface and the Neuroscience Gateway, without needing FPGA expertise. The same API runs networks locally for development or dispatches them to the hardware for scale, and users can modify synaptic weights on the fly. This combination of reconfigurable hardware, sparse event-driven computation, and open access gives the neuromorphic research community a testbed for exploring brain-scale spiking networks. Visit EmergentMind.com to dive deeper into the architecture and create your own video exploring event-driven neuromorphic computing.
