Threshold-Ordinal Surface (TOS)

• Threshold-Ordinal Surface (TOS) is an event-driven, ordinal-valued representation that encodes temporal recency to enable fast, decoupled corner detection in event-based cameras.
• It updates pixel values using an age-based decrement mechanism, transforming asynchronous events into a pseudo-intensity image suitable for standard Harris corner detection.
• The NMC-TOS architecture leverages near-memory computing and DVFS to accelerate patch updates and reduce energy consumption, crucial for real-time edge processing.

The Threshold-Ordinal Surface (TOS) is an event-driven, ordinal-valued representation developed for efficient corner detection in event-based camera (EBC) vision systems. It encodes the temporal "novelty" or recency of events at each pixel, facilitating the use of standard corner detection algorithms in the asynchronous data regime characteristic of EBCs. TOS supersedes traditional time-stamp-based surfaces by offering a pseudo-intensity image amenable to fast, decoupled corner detection and hardware acceleration, notably within near-memory architectures for edge computing environments (Shang et al., 2 Dec 2025).

1. Motivation and Representation

The TOS model addresses core limitations of the classical Surface of Active Events (SAE) in corner detection for EBC data. Because EBCs emit events only on brightness changes, pixel-wise time stamps inadequately capture local structure critical for corner detection. TOS replaces this with an 8-bit unsigned integer at every pixel, which is updated to reflect how recently an event occurred.

Upon arrival of a new event $v = (v_x, v_y, v_t)$, a local $P \times P$ patch centered at $(v_x, v_y)$ is aged: each pixel in the patch decrements its TOS value by one. If the decremented value falls below a threshold TH (e.g., $\mathrm{TH} \approx 225$), it is set to zero. The central pixel’s TOS value is then reset to 255, indicating maximal novelty. This operation transforms the event stream into a spatially localized, ordinal surface encoding recency, approximating a synthetic intensity image suitable for classical frame-based operators (Shang et al., 2 Dec 2025).

2. Mathematical Formulation and Update Mechanism

Formally, for event $v_k = (x_k, y_k, t_k)$ and patch half-width $h = (P-1)/2$, the update for TOS at pixel $(x, y)$ after the $k$th event is:

$$TOS(x,y;k) = \begin{cases} 255, & (x,y) = (x_k, y_k) \ \max\left( TOS(x,y;k-1) - 1, 0 \right), & (x,y) \in \Omega_k,\, TOS(x,y;k-1) - 1 \geq TH \ 0, & (x,y) \in \Omega_k,\, TOS(x,y;k-1) - 1 < TH \ TOS(x,y;k-1), & (x,y) \notin \Omega_k \end{cases}$$

where $$\Omega_k = \{ (x,y) \mid |x-x_k| \leq h,\, |y-y_k| \leq h \}$$ is the patch support (Shang et al., 2 Dec 2025).

Pseudocode (“Algorithm 1” in (Shang et al., 2 Dec 2025)) for event-wise updates is as follows:

for x = v_x - h to v_x + h: for y = v_y - h to v_y + h: TOS[x, y] ← TOS[x, y] - 1 if TOS[x, y] < TH: TOS[x, y] ← 0 TOS[v_x, v_y] ← 255

This process is computationally $O(P^2)$ per event in a naïve implementation.

3. Corner Detection Using TOS

After TOS has been updated for each new event, corner detection is performed in a frame-by-frame (FBF) mode using the latest TOS as the pseudo-intensity image $I(x, y) = TOS(x, y)$. The standard Harris corner score is calculated by:

$$G_x(x, y) = \frac{\partial I}{\partial x},\quad G_y(x, y) = \frac{\partial I}{\partial y}$$

with derivatives typically approximated by $3\times3$ Sobel filters.

A support window $W$ (frequently $5\times5$) yields the structure tensor: $$M(x, y) = \sum_{(u,v) \in W} \begin{pmatrix} G_x(u, v)^2 & G_x(u, v) G_y(u, v) \ G_x(u, v) G_y(u, v) & G_y(u, v)^2 \end{pmatrix}$$

The Harris score is then: $R(x, y) = \det M - k (\mathrm{trace}\,M)^2$ with $k \approx 0.04$–$0.06$.

To quickly label events as corners, the pattern of $R$ values can be pre-computed into a lookup table (LUT) at each frame. For methods such as luvHarris, this enables $O(1)$ tagging of corner events (Shang et al., 2 Dec 2025).

4. Hardware Architecture: Near-Memory TOS (NMC-TOS)

Resource-constrained edge devices processing dense event streams face latency bottlenecks due to the $O(P^2)$ patch update per event. The NMC-TOS architecture applies near-memory computing to mitigate this.

Key features include:

• Read-write decoupled 8T SRAM cells (Type A): Enable pipelined processing of each patch row, reducing cycle wait from $O(P \cdot (t_1 + t_2 + t_3 + t_4))$ to $P \cdot (t_1 + t_2) + t_3 + t_4$ (~2× improvement).
• Minus-One Logic (MOL) module: Custom hardware for decrementing TOS values, exploiting the -1 operation to simplify the adder and reduce delay by ≈30% relative to standard full adders.
• Bit-wise comparison (CMP) module: NAND logic for low-power thresholding of TOS values, using compact 2-row 8T SRAM Type B.
• Four-stage pipelined row processing: Pre-charge (PCH), minus-one (MO), compare (CMP), write-back (WR) stages interleaved across patch rows, reducing per-event update latency from ≈392 ns (conventional, 500 MHz) to 16 ns at 1.2 V (203 ns at 0.6 V).
• Storage optimization: Storing only the lowest 5 bits per 8-bit TOS value (exploiting high TH) saves ≈37.5% SRAM with reconstruction when required.
• Dynamic Voltage and Frequency Scaling (DVFS): An event-rate estimator adjusts VDD and $f_{CLK}$ to minimize energy at low event rates (0.6 V) and increase throughput for bursts (up to 1.2 V) (Shang et al., 2 Dec 2025).

5. Empirical Performance and Robustness

Experimental validation demonstrates that NMC-TOS significantly accelerates event patch updates and reduces energy consumption:

Implementation	Latency (7×7)	Throughput (Meps)	Energy per Update	BER at VDD (≥0.62/0.61/0.60 V)
Conventional digital	392 ns	2.6	Baseline	0 / - / -
NMC-TOS, 1.2 V	16 ns	63.1	1.2× less	0 / - / -
NMC-TOS, 0.6 V	203 ns	4.9	6.6× less	0 / 0.2% / 2.5%

Corner detection precision-recall AUC drops by only 0.027 (“shapes_dof”) and 0.015 (“dynamic_dof”) at 2.5% BER (0.015 and unchanged at 0.2% BER) under worst-case hardware non-idealities, demonstrating that the impact of low-voltage bit errors is minor, since only TOS values in 224–255 are affected (Shang et al., 2 Dec 2025).

6. Context and Significance

TOS offers a lightweight, efficient ordinal surface for asynchronous visual processing from event cameras, enabling the direct use of established frame-based corner detectors in the event-driven paradigm. This hybrid approach simplifies system integration and computational design for embedded systems. The NMC-TOS architecture reduces update latency by more than 20× and energy by up to 6.6× (with DVFS enabled), with minimal degradation in detection performance, thus addressing a primary bottleneck for real-time event-driven computer vision at the edge (Shang et al., 2 Dec 2025). A plausible implication is that such trends in in-memory and near-memory event-surface computations will be increasingly critical for bridging the performance gap between biological and artificial vision sensors in wearable, surveillance, and autonomous robotics domains.