Three-Stage Rasterization Pipeline

• Three-stage rasterization pipeline is a framework that divides image synthesis into vertex processing, rasterization with depth testing, and fragment shading.
• It processes polygonal scenes by applying geometric transforms, spatial binning, and per-pixel computations to optimize memory usage and parallelism.
• Applications in MobileNeRF, Piko, and CuRast demonstrate its extensibility, enabling both traditional and neural rendering techniques in modern graphics.

A three-stage rasterization pipeline is a canonical framework for implementing image synthesis of polygonal scenes, systematically dividing rendering into a sequence of geometric and fragment-processing transformations. This architecture appears consistently in both classic and modern graphics systems, from graphics hardware to programmable software rasterizers and neural field acceleration techniques. Each stage encapsulates distinct linear algebraic, geometric, or per-sample operations, offering a well-defined point for parallelization, memory optimization, and extensibility, as demonstrated in frameworks like Piko (Patney et al., 2014), MobileNeRF (Chen et al., 2022), and CuRast (Schütz et al., 23 Apr 2026).

1. Stages of the Classic Rasterization Pipeline

The canonical three-stage pipeline comprises:

1. Vertex Processing: Transformation of vertices from model to screen space, geometric culling, and attribute setup.
2. Rasterization and Z-Buffering: Conversion of triangles into per-pixel fragments, interpolation of attributes, and visibility determination via depth (Z-buffering).
3. Fragment (or Pixel) Shading: Computation of final pixel color via per-fragment attribute evaluation, texturing, shading, or neural decoding.

Each stage exploits parallelism and often relies on spatial binning (also termed "tiling") to optimize throughput, memory locality, and balancing of thread workloads (Patney et al., 2014).

2. Detailed Stage Functionality and Dataflows

2.1 Vertex Processing

• Transformations: Vertices undergo a pipeline of model, view, and projection transforms. For homogeneous coordinates, $$p_\text{clip} = P \cdot V \cdot M \cdot p_\text{model}$$, followed by normalization for device and screen mapping as $p_\text{ndc} = p_\text{clip}/p_\text{clip}.w$ (Chen et al., 2022).
• Culling: Triangles are eliminated if outside the frustum or back-facing (Patney et al., 2014).
• Prim Encoding: Extended pipelines, such as MobileNeRF, bake non-standard data—e.g., binary opacities $\alpha \in \{0,1\}$ and high-dimensional features $f\in[0,1]^8$—into per-vertex textures (Chen et al., 2022).
• Spatial Binning: Triangles are assigned to image-space tiles to facilitate parallel per-tile operations in subsequent stages; tile indices are computed from bounding-box partitions (Patney et al., 2014).

2.2 Rasterization and Z-Buffering

• Fragment Generation: For each image tile/bin, all triangles overlapping its region are rasterized, generating per-pixel fragments with interpolated attributes (e.g., depth, normals) (Patney et al., 2014).
• Depth Test: Z-values are compared, with only the closest fragments processed further. Z-buffering is commonly implemented as either hardware-accelerated or with atomic operations in CUDA pipelines (e.g., atomicMin on 64-bit packed depth plus triangle ID in CuRast) (Schütz et al., 23 Apr 2026).
• Attribute Interpolation: Attributes are linearly interpolated using barycentric coordinates—$w_1, w_2, w_3$—to yield, e.g., $f_\text{interp} = w_1 f^1 + w_2 f^2 + w_3 f^3$ (Chen et al., 2022).
• Deferred Feature Images: In pipelines such as MobileNeRF, rasterization produces a "feature image" holding high-dimensional features, opacities, and view directions for each pixel (Chen et al., 2022).

2.3 Fragment Shading

• Shading Equation: Classical shading applies lighting models (e.g., Lambertian), typically performed per fragment (Patney et al., 2014).
• Custom Decoders: In neural rasterizers (MobileNeRF), a miniature MLP $$H: \mathbb{R}^8 \times \mathbb{R}^3 \rightarrow [0,1]^3$$ is invoked for pixels with interpolated $\alpha > 0.5$, decoding learned features and view direction into color (Chen et al., 2022).
• Visibility Control: Only fragments passing opacity/depth thresholds are shaded.

3. Variants and Parallelization Strategies

Rasterization pipelines may diverge in scheduling, memory layout, and specialization for hardware or software:

• Spatial Binning: Binning into $B_w \times B_h$ tiles enables efficient per-bin scheduling, crucial for modern GPUs and multicore CPUs (Patney et al., 2014).
• Scheduling Policies:
  • LoadBalance: GPU scheduling distributes bins dynamically across CUDA blocks for high occupancy.
  • DirectMap: For CPUs, tiles are statically assigned to cores to preserve producer–consumer locality and reduce memory latency.
• Kernel Fusion: Pipelines like Piko can fuse adjacent stages (e.g., vertex shading and tile raster) if scheduling and binning align, minimizing memory traffic (Patney et al., 2014).
• Work Granularity Tuning: Trade-offs exist between small bins (maximizing parallelism and locality but increasing overhead) and large bins (reduced overhead but risk load imbalance) (Patney et al., 2014).

CuRast introduces a data-driven classification of triangles by screen-space size, assigning "tiny," "medium," and "large" triangles to increasingly heavyweight CUDA kernels: one thread per triangle, one warp per triangle, or one block per triangle-tile, respectively (Schütz et al., 23 Apr 2026). This workload stratification concentrates most work in the highly parallel, single-thread stage, with queues staging oversized triangles to following stages only as necessary.

4. Applications in Modern Systems

Rasterization for Photorealistic Neural Rendering

MobileNeRF reformulates NeRF field rendering to fit within standard polygon rasterization, including:

• Baking neural features and binary opacities into triangle textures.
• Rasterizing with z-buffering to produce feature images.
• Applying per-pixel, tiny MLP decoders in fragment shaders (Chen et al., 2022).

This approach permits real-time neural synthesis on commodity hardware (e.g., 744.9 FPS on RTX 2080Ti for $800\times800$ images) while drastically reducing GPU memory requirements compared to earlier NeRF implementations.

High-Performance Software Rasterization on GPUs

CuRast demonstrates efficient CUDA-based rendering of billion-triangle datasets without acceleration structures by exploiting the three-stage model. On dense, photogrammetric models, it achieves 2–5× speedup over Vulkan for unique geometry and up to 12× for instanced meshes, handling 13.6 billion triangles in under 75 ms in its fast path (Schütz et al., 23 Apr 2026). Most triangles (90%+) are processed as "tiny" via a single-thread kernel, amortizing setup and maximizing GPU throughput.

Programmable Graphics Pipeline Design

Piko presents a template-based, architecture-retargetable pipeline in which bin size and scheduling can be tuned for a target device. It supports not only classic rasterization but also hybrid, ray tracing, and deferred rendering, all expressible as three-stage or multi-stage bin/schedule/process decompositions. Performance is typically within a factor of 3–6 of hand-tuned CUDA rasterizers, with significant gains in design flexibility (Patney et al., 2014).

5. Performance, Trade-Offs, and Limitations

Performance and efficiency of the three-stage pipeline are dictated by:

• Stage Skew: On dense scenes, the earliest stage may dominate (e.g., Stage 1 accounts for most time in CuRast for massive meshes), whereas later stages incur microseconds unless exceptional geometry passes through (Schütz et al., 23 Apr 2026).
• Pipeline Fusion and Locality: Fusing kernels via spatial bin and schedule alignment can preserve cache locality and decrease main-memory pressure, as observed in Piko for CPU retargeting (Patney et al., 2014).
• Bin Size and Scheduling: Small bins enhance locality and parallelism but increase atomic bin assignment cost; large bins risk imbalanced workloads (Patney et al., 2014).
• Limiting Factors: Transparency, blending, and support for thousands of low-poly meshes remain challenging; they typically necessitate new pipeline stages (e.g., transparent pass or depth peeling) or hybrid methods (Schütz et al., 23 Apr 2026).
• Acceleration Structures: Unlike classical approaches, modern pipelines (CuRast) eschew construction of BVH or grids, leveraging brute-force atomicMin-based depth tests and multi-stage queuing for scale, benefiting real-time editability and animation (Schütz et al., 23 Apr 2026).

6. Comparative Summary Table

Pipeline	Stage 1 (Vertex/Setup)	Stage 2 (Rasterize/Bin)	Stage 3 (Fragment Shade)
MobileNeRF (Chen et al., 2022)	Model→view→clip, mesh+features bake	Rasterize, z-buffer, feature image	Per-pixel MLP decode in shader
Piko (Patney et al., 2014)	Vertex shading, culling, binning	Tile rasterization, per-bin listing	Per-fragment classic shading
CuRast (Schütz et al., 23 Apr 2026)	"Tiny"-triangle one-thread kernel	"Medium" per-warp rasterization	"Large" per-block tile intersection

The table summarizes the division of computational roles for each referenced system, emphasizing that the classic three-stage structure serves as a flexible abstraction for both traditional and data-driven rendering.

7. Research Directions and Extensions

Current and future work includes the addition of transparency support (potentially via distinct depth-peeling or accumulation stages), better handling of low-poly, multi-mesh scenes through enhanced bin management or hybrid software/hardware delegation, and integration of hierarchical LOD (e.g., mesh cluster-based level-of-detail control) (Schütz et al., 23 Apr 2026). In programmable frameworks, the exploration of kernel fusion strategies, adaptive bin sizing, and dynamic scheduling remains an active axis for optimizing spatial and producer-consumer locality (Patney et al., 2014).

A plausible implication is that continued refactoring of neural, photogrammetric, and programmable rasterization into three-stage models benefits from persistent advances in parallel scheduling, in-place kernel fusion, and strategic memory layout—thus maintaining relevance as hardware and scene complexity increase.