3D-ICE 4.0 Thermal Modeling Framework

• The paper introduces 3D-ICE 4.0, a finite-difference/RC solver that accurately addresses transient heat conduction while preserving detailed layout heterogeneity via quadtree tiling.
• It demonstrates significant performance gains by reducing matrix assembly time from hundreds of seconds to 0.8 s on 7 cores and lowering memory usage by over 27% compared to PACT.
• The framework employs adaptive vertical partitioning and temperature-aware non-uniform grid generation to cut discretization error by more than 23% without compromising accuracy.

Searching arXiv for the exact topic and nearby uses of the same term. 3D-ICE 4.0 is a thermal modeling framework for advanced 2.5D/3D heterogeneous chiplet systems, introduced as an accurate and efficient alternative to compact thermal models that often struggle to scale with the complexity and heterogeneity of modern architectures (Zhu et al., 5 Dec 2025). It is a Finite-Difference/RC-network–based solver for the transient heat equation in three dimensions, with three stated innovations: preservation of material heterogeneity and anisotropy directly from industrial layouts, adaptive vertical layer partitioning for vertical heat conduction, and temperature-aware non-uniform grid generation. The framework is designed to produce detailed thermal maps with high computational efficiency, and its reported evaluations compare it both to the state-of-the-art tool PACT and to the commercial finite-element package COMSOL (Zhu et al., 5 Dec 2025).

1. Governing formulation and physical scope

3D-ICE 4.0 solves the transient heat equation

$$\rho(\mathbf x)\,c_p(\mathbf x)\,\frac{\partial T(\mathbf x,t)}{\partial t} \;-\; \nabla\!\cdot\!\bigl(k(\mathbf x)\,\nabla T(\mathbf x,t)\bigr) \;=\;Q(\mathbf x,t),$$

where $\rho\,c_p$ is the volumetric heat capacity, $k$ is the possibly anisotropic thermal conductivity tensor, $Q$ is the volumetric heat injection rate, and $T(\mathbf x,t)$ is the temperature field (Zhu et al., 5 Dec 2025).

The boundary conditions described for the framework include top and bottom convection,

$$-\,\mathbf n\cdot k\,\nabla T \;=\;h\bigl(T - T_\infty\bigr) \quad\text{on exposed surfaces,}$$

with $h$ the heat-transfer coefficient and $T_\infty$ the ambient. Adiabatic or symmetry boundary conditions are used on lateral faces as required by the package geometry (Zhu et al., 5 Dec 2025).

After discretization and RC-matrix assembly, the steady-state or implicit-time-step problem is written as

$$\mathbf C\,\frac{\Delta\mathbf T}{\Delta t} + \mathbf G\,\mathbf T = \mathbf Q,$$

where $\mathbf C$ is the capacitance matrix and $\rho\,c_p$0 the conductance, or Laplacian, matrix (Zhu et al., 5 Dec 2025). This places the framework within the established RC-network tradition of thermal simulation, but with a more explicit treatment of layout-level heterogeneity and anisotropy than is typical of homogenized compact models. This suggests that its principal objective is not merely faster solution of a reduced thermal network, but a closer correspondence between layout detail and the thermal discretization.

2. Layout-faithful representation of heterogeneity and anisotropy

A defining feature of 3D-ICE 4.0 is direct GDSII import. Rather than homogenizing each layer by volume-fraction averaging, the framework uses a quadtree tiling procedure to partition each metal, polymer, or underfill layer into small rectangular tiles (Zhu et al., 5 Dec 2025).

For each tile, the overlap ratio with GDSII polygons is computed and an equivalent thermal conductivity $\rho\,c_p$1 is assigned so as to preserve both in-plane and through-plane anisotropy, including structures such as microbump arrays and TSV forests (Zhu et al., 5 Dec 2025). The stated purpose is preservation of material heterogeneity and anisotropy directly from industrial layouts.

The reported thermal consequence of this modeling choice is non-negligible. In a 4-chiplet example, a homogenized model predicts a hotspot of 390.15 K, whereas the detailed heterogeneous model gives 394.22 K, corresponding to a $\rho\,c_p$2 of approximately 4 K (Zhu et al., 5 Dec 2025). In this comparison, the discrepancy is attributable to the loss of explicit spatial heterogeneity in the homogenized treatment. A plausible implication is that layout-averaged conductivities can underestimate peak temperature when lateral and vertical heat-flow paths are strongly modulated by local interconnect and packaging structure.

The same comparison to COMSOL is used to support a second point: 3D-ICE 4.0 is reported to capture both lateral and vertical heat flows effectively (Zhu et al., 5 Dec 2025). In the paper’s framing, the framework’s fidelity depends on retaining the geometric and material distinctions that govern these coupled flows, rather than collapsing them into coarse effective layers.

3. Numerical solution strategy and parallel performance

The implementation parallelizes all loops over elements and tiles with OpenMP tasks, and invokes the multi-threaded SuperLU MT library for symbolic factorization, numeric factorization, and triangular solves (Zhu et al., 5 Dec 2025). The framework therefore couples a structured thermal discretization pipeline to shared-memory parallel assembly and sparse direct linear algebra.

The assembly-time reduction reported in the paper is substantial: matrix assembly decreases from hundreds of seconds to approximately 0.8 s on 7 cores, versus 148.2 s in PACT (Zhu et al., 5 Dec 2025). Across 1–32 cores, the use of SuperLU MT yields speedups of 3.61x–6.46x over PACT, with parallel efficiency maintained up to approximately 30 threads (Zhu et al., 5 Dec 2025).

On a 2.5 million–unknown problem, 3D-ICE 4.0 runs in 147 s on 7 cores, whereas PACT requires 949 s, with both timings including assembly and solve (Zhu et al., 5 Dec 2025). Peak memory is reported as 35.3 GB, which is 27.3% lower than PACT’s 48.4 GB (Zhu et al., 5 Dec 2025). The paper also reports a grid sweep in which, for 256×256 up to 2.5 M unknowns, 3D-ICE 4.0 is 1.5x–2x faster than PACT on the same cores (Zhu et al., 5 Dec 2025).

These results locate 3D-ICE 4.0 in a specific methodological niche: it is not presented as a reduced-order surrogate, but as a high-fidelity solver whose efficiency derives from parallel assembly, sparse direct solution, and adaptive discretization. This suggests that the framework targets workloads where the dominant constraint is turnaround time for detailed package-level thermal analysis rather than minimal model order.

4. Adaptive vertical layer partitioning

The framework introduces adaptive vertical layer partitioning to address the inadequacy of assigning a single RC layer to each functional die, TIM, interposer, or related stack component. The stated motivation is that a single RC layer per functional die yields very non-uniform vertical resistances, so CTMs under-resolve cross-layer gradients (Zhu et al., 5 Dec 2025).

For each original layer $\rho\,c_p$3 with subareas $\rho\,c_p$4, the formulation defines

$\rho\,c_p$5

and

$\rho\,c_p$6

followed by the variance metric

$\rho\,c_p$7

The algorithm then selects the layer or layers with largest $\rho\,c_p$8 or highest contribution to $\rho\,c_p$9, splits them into two or more sublayers of half thickness, recomputes resistances, and repeats until the variance falls below a threshold or a maximum depth is reached (Zhu et al., 5 Dec 2025).

The reported accuracy gains are benchmarked against COMSOL. In a 2.5D chiplet stack, the case with no division, described as one layer per functional block, yields RMSE greater than 4 K in hot regions (Zhu et al., 5 Dec 2025). After 8 iterations, with the chip divided into 2 layers and TIM and PCB into 4 layers each, layer RMSE falls below 0.5 K, and the vertical slice of $k$0 nearly overlaps COMSOL (Zhu et al., 5 Dec 2025).

The same section reports transient validation using Gaussian-modulated sinusoidal power at two observation points. After layer division, the model exhibits sub-1 K amplitude error and correct phase (Zhu et al., 5 Dec 2025). In the logic of the paper, adaptive splitting is therefore not merely a refinement of vertical mesh density; it is a targeted correction for the mismatch between heterogeneous through-plane conductance and overly coarse RC layering.

5. Temperature-aware non-uniform grid generation

3D-ICE 4.0 also introduces temperature-aware non-uniform grid generation. The workflow is described in three stages: first solve on a coarse uniform mesh, then compute the per-tile average temperature gradient $k$1, and finally refine tiles with large $k$2 by splitting their $k$3 dimensions (Zhu et al., 5 Dec 2025). The method is explicitly temperature-aware because the refinement criterion is derived from an initial thermal solution rather than from geometry alone.

The quantitative benefit is presented through a one-die local-grid benchmark labeled Case 3. To reach RMSE below 0.3 K, a uniform mesh needs 11,760 cells, whereas the non-uniform mesh requires 8,714, a reduction of 25.9% (Zhu et al., 5 Dec 2025). For RMSE below 0.25 K, the number of cells drops from 15,360 to 11,787, corresponding to a reduction of 23.3% (Zhu et al., 5 Dec 2025). Peak pointwise error decreases from approximately 1 K to approximately 0.6 K by focusing resolution on hotspots (Zhu et al., 5 Dec 2025).

These results are consistent with the broader claim in the abstract that grid complexity is reduced by more than 23.3% without compromising accuracy (Zhu et al., 5 Dec 2025). A plausible implication is that the framework’s performance gains do not arise solely from solver parallelism; they also depend on concentrating spatial resolution in regions where thermal gradients dominate the error budget.

The combined picture is that 3D-ICE 4.0 uses two distinct adaptivity mechanisms. Vertical adaptivity addresses cross-layer resistance variance, while lateral non-uniform meshing is driven by temperature gradients. The paper treats these as complementary, rather than interchangeable, remedies for discretization error.

6. Validation, assumptions, limitations, and nomenclature

The paper reports three benchmark classes: comparison against PACT, comparison against COMSOL on a 2.5D chiplet stack, and a local-grid study on a single die (Zhu et al., 5 Dec 2025). The principal reported results are summarized below.

Benchmark	Reported result	Reference
PACT comparison	3.61x–6.46x faster on 1–32 cores; 35.3 GB vs. 48.4 GB	(Zhu et al., 5 Dec 2025)
COMSOL comparison	Lateral and vertical temperature within 0.5 K in steady state; transient sub-1 K error with correct phase	(Zhu et al., 5 Dec 2025)
Local-grid study	23.3% to 25.9% fewer unknowns for the same error budget; peak error down by about 40%	(Zhu et al., 5 Dec 2025)

The assumptions stated for the current implementation are that material properties $k$4, $k$5, and $k$6 are taken constant with temperature and from literature, that the convective boundary uses uniform $k$7, and that radiation and fluid-flow coupling are not included (Zhu et al., 5 Dec 2025). The listed limitations are that the current CTM cannot capture very rapid power-temperature coupling in the sub-microsecond regime where wave effects might matter, and that there is no built-in support for on-chip microfluidic cooling or phase-change materials (Zhu et al., 5 Dec 2025).

The future extensions named in the paper are GPU-accelerated RC assembly and solve, automatic coupling with CFD solvers for advanced cooling, machine-learning–aided grid-refinement heuristics beyond pure gradient metrics, and inclusion of temperature-dependent material properties for more extreme thermal excursions (Zhu et al., 5 Dec 2025). The code and examples are stated to be available open-source at the EPFL repository for 3D-ICE (Zhu et al., 5 Dec 2025).

The term “3D-ICE 4.0” is not unique across scientific domains. In IceCube literature, it is also used as shorthand for the SPICE FTP v3 framework plus ancillary refinements for the three-dimensional optical response of South Pole ice (Chirkin et al., 8 Jul 2025), and a separate IceCube cosmic-ray reconstruction report uses the same label for a unified likelihood fit of IceTop and in-ice observables (Bai et al., 2019). This nomenclatural overlap is bibliographically relevant, but it refers to unrelated modeling problems. In semiconductor thermal modeling, “3D-ICE 4.0” denotes the heterogeneous chiplet thermal framework described above (Zhu et al., 5 Dec 2025).