Brainstacks: Layered Brain-Inspired Architectures

• Brainstacks is a term for diverse layered structures in brain-inspired computing, including literal assembly stacks, neuromorphic technology layers, continual-learning adapters, and memory hierarchies.
• They employ common design motifs such as selective routing and plasticity–stability trade-offs to ensure robust operation and efficient computation.
• Applications span from autonomous AI memory systems and neuromorphic processors to advanced LLM tuning, each leveraging precise control across computational layers.

“Brainstack” and “Brainstacks” are labels used in several brain-inspired computing literatures for stack-structured or layered organizations of representation, plasticity, and control, but they do not denote a single standardized architecture. In “Planning with Biological Neurons and Synapses,” a Brainstack is a stack data structure implemented as a chain of assemblies in the Assembly Calculus (d'Amore et al., 2021). In “Thermodynamic-RAM Technology Stack,” “Brainstacks” names the eight-layer neuromorphic technology stack spanning memristor device physics through server-level software (Nugent et al., 2014). In “Brainstacks: Cross-Domain Cognitive Capabilities via Frozen MoE-LoRA Stacks for Continual LLM Learning,” the term refers to frozen domain-specific adapter stacks composed additively on a shared frozen base model (Ayyash, 1 Apr 2026). In “ZenBrain: A Neuroscience-Inspired 7-Layer Memory Architecture for Autonomous AI Systems,” it denotes a seven-layer memory hierarchy governed by neuroscience-inspired algorithms and Predictive Memory Architecture components (Bering, 26 Apr 2026).

1. Terminological scope and recurring structure

The literature assigns “Brainstack” to distinct technical objects: a symbolic data structure realized in spiking assemblies, a hardware-software abstraction stack for neuromorphic processors, a continual-learning adapter stack for LLMs, and a layered memory architecture for autonomous agents. The commonality is structural rather than ontological: each usage organizes computation into vertically composed levels or states with controlled transitions, selective routing, and explicit plasticity–stability management.

Context	Meaning of “Brainstack(s)”	Source
Assembly Calculus	A stack implemented as a chain of assemblies in five brain areas	(d'Amore et al., 2021)
Thermodynamic-RAM	The eight layers of a neuromorphic technology stack	(Nugent et al., 2014)
Continual LLM learning	Frozen domain-specific MoE-LoRA stacks on a frozen base	(Ayyash, 1 Apr 2026)
ZenBrain	A seven-layer memory hierarchy for autonomous AI systems	(Bering, 26 Apr 2026)

A useful distinction is between literal stacks and abstraction stacks. The Assembly Calculus Brainstack is a literal push/pop data structure. Thermodynamic-RAM uses the term for a bottom-up implementation hierarchy. The 2026 Brainstacks architecture uses additive frozen stacks of adapters, while ZenBrain uses stacked memory stores with consolidation, decay, and reconsolidation. This suggests that the term functions as a family resemblance label for brain-inspired layering rather than as a canonical formalism.

2. Brainstack as a neural stack in the Assembly Calculus

In the Assembly Calculus model, each brain area $A$ consists of $n$ excitatory neurons with random connectivity $P(x\to y \mid x,y\in A)=p$, and at most $k$ neurons may fire at any time step. An assembly is a set of size $k$ that, once formed, re-fires together when cued. Synaptic weights are initialized to $1$ and follow Hebbian plasticity:

$w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$

when neuron $x$ fires at time $t$ and neuron $y$ fires at time $n$0 (d'Amore et al., 2021).

A stack of blocks $n$1 is encoded using five areas: Blocks, Head, and three node areas $n$2. Blocks contains a fixed pre-wired assembly $n$3 for each block $n$4. Parsing the stack projects each block from Blocks into the node areas in cyclic order, after which the node area projects into Head. The resulting representation is a chain of linked assemblies in which each node-area assembly is strongly connected both to its predecessor and to the block assembly representing the corresponding block. The bottom-to-top block order is therefore recapitulated as a sequence of linked assemblies.

Push and pop are realized through sequences of disinhibition and projection. For pop, Head is linked to node $n$5, Head$n$6node$n$7 and node%%%%19$\Delta_i(x)= s\cdot B_i(A_i x).$19%%%%9node$P(x\to y \mid x,y\in A)=p$0 are disinhibited, and $P(x\to y \mid x,y\in A)=p$1 is invoked. At the next time step, node$P(x\to y \mid x,y\in A)=p$2 fires, cued both by node$P(x\to y \mid x,y\in A)=p$3 and by residual chain connections; a subsequent projection from node$P(x\to y \mid x,y\in A)=p$4 to Head makes Head adopt the assembly one level down the stack. The top link is not erased, but it becomes unused. For push, Blocks$P(x\to y \mid x,y\in A)=p$5node$P(x\to y \mid x,y\in A)=p$6 is disinhibited, the new block assembly is projected into node$P(x\to y \mid x,y\in A)=p$7, then node%%%%20$\Delta_i(x)= s\cdot B_i(A_i x).$20%%%%9Head is projected so that Head fires the new block assembly; a cleanup strong projection across all five areas restores the chain order.

The synaptic substrate is $k$0 both within areas and across fibers. If $k$1 is the adjacency matrix from area $k$2 to area $k$3, then projection forms a dense subgraph between the active source and target assemblies, with the submatrix $k$4 containing nearly all ones up to a small fraction $k$5. After $k$6 projection rounds,

$k$7

for $k$8 and $k$9, so future firing of $k$0 recruits $k$1 with probability $k$2.

The central empirical limitation is chain reliability. Classical Assembly Calculus conditions require

$k$3

With $k$4, $k$5, $k$6, and $k$7, simple projections used in parsing, push, and pop are “essentially fool-proof” with $k$8. However, chaining $k$9 consecutive projections degrades substantially: beyond $1$0 blocks, the probability of fully recovering the chain drops below $1$1, even though $1$2 disjoint assemblies could coexist. The experiments also show an optimal window of $1$3 around $1$4 for maximizing chain length. In this usage, Brainstack is therefore a biologically plausible data structure whose main bottleneck is reliable long-chain recovery rather than single-operation correctness.

3. Brainstacks as the Thermodynamic-RAM technology stack

In Thermodynamic-RAM, “Brainstacks” refers to eight layers of abstraction needed to implement a neuromorphic processor based on AHaH Computing and integrate it into digital systems (Nugent et al., 2014). The stack runs bottom-up from device physics to application-facing infrastructure:

• Memristor device physics: a memristor is modeled as probabilistic two-state “metastable switches” in parallel with a Schottky-diode term, with total current

$1$5

where $1$6.

• Synapse implementation: a synapse is a differential pair of memristors $1$7 sharing a common node, with a two-phase “2-1” read/write cycle and qualitative update rule

$1$8

• AHaH node behavior: an AHaH node aggregates $1$9 synapses onto a common electrode $w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$0, with read-phase analog dot product

$w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$1

and unsupervised write feedback $w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$2.

• kT-RAM core architecture: a modified RAM array in which each cell stores a synapse rather than a bit, and an H-tree interconnect ties selected memristors to global lines $w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$3, $w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$4, and $w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$5.
• AHaH instruction set semantics: 12 forward/reverse instructions, including FF, FH, FL, FU, FA, FZ and RF, RH, RL, RU, RA, RZ.
• Sparse spike encoding scheme: each time step activates exactly $w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$6 out of $w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$7 channels, with input

$w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$8

reducing synapse activations to $w_{x\to y}\leftarrow (1+\beta)\,w_{x\to y}$9 rather than $x$0.

• kT-RAM emulator: a cycle-accurate software model with the same API as future hardware.
• SENSE server integration: a daemon linking spike encoders, buffers, virtual AHaH nodes, and application logic.

The stack’s main systems claim is collapse of the memory–compute barrier. Every access both reads and updates the model. On the device side, the target thresholds for synaptic updates are below $x$1, with $x$2 or greater, short pulse operation in the ps–ns regime, femto–picojoule updates, and retention ranging from seconds to weeks depending on application. At the node level, analog read+write occurs every cycle, giving “minimal per-sample energy at $x$3pJ level.” At the core level, kT-RAM targets semiconductor-speed read–write cycles in the GHz range with sub-pJ per synapse access.

Architecturally, the system avoids naive crossbar sneak paths through per-cell switches and explicit addressing, and it uses temporal partitioning so that multiple virtual AHaH nodes share the same H-tree by time-multiplexing disjoint sets of synapse addresses. The cost is controller complexity, multiplexing overhead, and sensitivity to device noise, parasitic capacitances, and ADC/DAC resolution. The emulator demonstrates a linear classifier on MNIST with $x$4 accuracy, while SENSE server integration is reported to keep host CPU utilization at $x$5 cycles because core adaptation is off-loaded.

In this usage, Brainstacks is not a data structure but a complete implementation hierarchy: materials, circuits, nodes, cores, ISA, encoding, emulation, and deployment.

4. Brainstacks as frozen MoE-LoRA stacks for continual LLM learning

The 2026 Brainstacks architecture defines a modular continual-learning system in which a pre-trained transformer base model is frozen throughout training and inference, while domain expertise is packaged into sequentially trained, permanently frozen adapter stacks (Ayyash, 1 Apr 2026). The base is TinyLlama-1.1B or Gemma 3 12B IT in 4-bit NF4 quantized form, implemented as bnb.nn.Linear4bit. Each domain-specific stack inserts MoE-LoRA delta modules into all seven transformer projections—$x$6, $x$7, $x$8, $x$9 in attention and gate, up, down in the FFN—at every layer. Inference is additive:

$t$0

Only the active stack receives gradients; frozen stacks are read-only and are offloaded to CPU half-precision to minimize GPU footprint.

Each LoRA expert uses low-rank factors $t$1 and $t$2 with rank $t$3. $t$4 is initialized to zero so that $t$5 begins at the identity, and rsLoRA uses $t$6 and scale $t$7, giving

$t$8

Routing is Shazeer-style noisy top-2 with $t$9 experts and $y$0 selected per token:

$y$1

followed by top-2 masking and softmax. The auxiliary load-balance loss is

$y$2

The training procedure has two nested loops. The inner loop performs residual boosting: add a new trainable MoE-LoRA stack, train it on domain data, freeze it, and stop if validation-loss improvement is below $y$3. The paper uses up to $y$4 rounds per domain and a BestStackCallback that restores the best checkpoint if validation loss spikes above $y$5 or plateaus for 4 evaluations. The outer loop orders domains by curriculum: Chat, Code, Math, Medical, Reasoning. Before each domain after the first, a null-space projector is computed from all frozen stacks using randomized SVD on $y$6 validation examples with $y$7:

$y$8

This constrains new stacks to operate in the orthogonal complement of prior domains and is stated to enforce zero forgetting by construction.

After supervised fine-tuning, the system trains an outcome-based sigmoid meta-router of approximately $y$9M parameters. The router consumes a weighted sum of hidden states, $n$00 mid-layer plus $n$01 last-layer, with all domain stacks disabled. It applies linear token projection to dimension $n$02, learned global query attention, cross-attention to per-domain query vectors, and a fusion MLP with GELU and dropout, ending in independent sigmoids rather than a softmax. The chat stack has a minimum weight of $n$03, and stack-loading threshold is $n$04. Outcome targets are discovered greedily by loss reduction of at least $n$05, with a soft-boost target $n$06 for any reasoning improvement and a final target $n$07. Training lasts 8 epochs with cosine learning-rate schedule and checkpoint selection by

$n$08

Empirically, parameter-matched MoE-LoRA converges faster per step than single LoRA: on Alpaca with TinyLlama-1.1B, single LoRA ($n$09, $n$10M parameters) reaches validation loss $n$11 in 400 steps and 9.5 minutes, while MoE-LoRA ($n$12, $n$13M parameters) reaches $n$14 in 400 steps and 20.2 minutes, but attains single LoRA’s final loss in $n$15 steps, i.e. $n$16 faster convergence per step. Residual boosting improves the chat domain from a single-LoRA plateau of $n$17 to a final $n$18, a $n$19 relative improvement. In 4-domain continual learning on TinyLlama, the reported final losses are Chat $n$20, Code $n$21, Medical $n$22, and Math $n$23, with 9 stacks total.

The paper’s most specific claim concerns interference and recovery. Ungated accumulation damages composition quality: after all domains, chat validation loss rises to $n$24 from $n$25 “purely by magnitude accumulation, not weight drift,” and ungated 10-stack generation collapses into over-thinking math chains on every prompt. Null-space training reduces interference, with chat loss after math equal to $n$26 with null-space versus $n$27 without it, $n$28. When the meta-router gates each domain in isolation, each domain’s loss returns exactly to its training-time value. On 33 medical prompts, an oracle uses only the medical stack in $n$29 of cases and chat+math stacks in $n$30 of cases despite zero medical data in those stacks, leading the paper to argue that the learned stacks encode transferable cognitive primitives such as instruction-following clarity, numerical reasoning, procedural logic, and chain-of-thought structure. A boundary RL experiment also exposes fragility: per-domain GRPO on code causes catastrophic spikes to $n$31 million loss, corrupting that stack and all downstream stacks, which motivates completing SFT stacking before any RL.

5. Brainstack as ZenBrain’s layered memory architecture

ZenBrain uses “Brainstack” to denote a seven-layer memory architecture for autonomous AI systems (Bering, 26 Apr 2026). The layers are Working, Short-Term, Episodic, Semantic, Procedural, Core, and Cross-Context memory. Working Memory holds up to $n$32 items at millisecond–second latency; Short-Term retains the current session’s context over minutes–hours; Episodic stores timestamped events; Semantic abstracts facts and relationships into a knowledge graph; Procedural stores skills and routines; Core pins identity and preference facts that never decay; Cross-Context performs privacy-aware entity resolution and selective transfer between isolated domains. A MemoryCoordinator orchestrates five operations across these layers: store, recall, consolidate, decay, and review.

The architecture is governed by nine foundational neuroscience algorithms. The Two-Factor Synaptic Model attaches to each knowledge-graph edge a weight $n$33 and variance $n$34, with importance $n$35, and updates them by

$n$36

This yields an EWC-style penalty $n$37 that protects mature edges. Other foundational mechanisms include the Ebbinghaus forgetting curve $n$38, vmPFC-coupled FSRS for review scheduling under context shift, a Simulation-Selection sleep loop that scores replay candidates by

$n$39

Bayesian confidence propagation, emotional arousal tagging, similarity clustering, context-retrieval that fuses BM25 and dense embeddings with per-layer boosts, and visualization indexing.

ZenBrain further adds six Predictive Memory Architecture components. The NeuromodulatorEngine maintains DA, NE, 5HT, and ACh with tonic baselines, phasic bursts, DA–5HT opposition of $n$40, and decay factor $n$41. ReconsolidationEngine makes retrieved memories labile and gates update modes by effective prediction error. TripleCopyMemory stores each event in three copies with divergent decay:

$n$42

with composite strength $n$43. PriorityMap computes

$n$44

and imposes an amygdala fast-path $n$45. StabilityProtector uses lock score $n$46 and rigidity $n$47 to gate overwrites, permitting updates only if

$n$48

MetacognitiveMonitor tracks confirmation, recency, and retrieval biases and opens 10-minute novelty windows after high-PE events above $n$49.

The empirical case for this Brainstack is explicitly comparative. Layered routing improves LoCoMo by $n$50 F1 over a flat single-layer baseline with $n$51, including $n$52 temporal F1, and improves MemoryArena by $n$53 F1 with $n$54, including $n$55 on dependency-chain questions. Simulation-Selection sleep yields a $n$56 stability improvement with $n$57 while reducing storage by $n$58. TripleCopyMemory retains $n$59, and PriorityMap achieves $n$60 versus chronological $n$61. The 15-algorithm ablation shows a cooperative survival network: under challenging conditions, seven algorithms become individually critical, including vmPFC-FSRS removal $n$62, TripleCopy $n$63, Dual-Process CoT $n$64, Two-Factor $n$65, IB Budget $n$66, Sleep $n$67, and Neuromodulator $n$68; under extreme stress, nine become critical, including StabilityProtector $n$69 and Reconsolidation $n$70. Removing all six PMA components collapses retention to floor by day 30, whereas the full system retains $n$71, a $n$72 advantage with $n$73.

At benchmark scale, ZenBrain also reports the highest mean rank on all 12 system-judge cells of LongMemEval-500, with three-judge mean $n$74 versus letta $n$75, a-mem $n$76, and mem0 $n$77; all 9 pair-wise contrasts clear Bonferroni. Under the binary judge, it reaches $n$78 of oracle accuracy at $n$79th the per-query token budget. In this usage, Brainstack names a memory hierarchy whose defining operations are consolidation, forgetting, reconsolidation, and bias-aware control rather than parameter-efficient adaptation or neuromorphic device composition.

6. Comparative interpretation, non-equivalence, and research significance

Across these works, the term identifies four different stack formalisms: a push/pop structure over assemblies, a full neuromorphic technology stack, a family of additive frozen adapter stacks for continual LLM tuning, and a seven-layer memory hierarchy for autonomous agents (d'Amore et al., 2021, Nugent et al., 2014, Ayyash, 1 Apr 2026, Bering, 26 Apr 2026). The label is therefore descriptive rather than taxonomic.

Three recurring design motifs nevertheless appear. First, all four systems make selective routing central: disinhibition of fibers and strong projection in Assembly Calculus, explicit A/B/y addressing plus sparse spike activation in kT-RAM, outcome-based sigmoid gating in the LLM architecture, and MemoryCoordinator plus per-layer retrieval boosts in ZenBrain. Second, each system confronts a plasticity–stability trade-off: chain-recovery failures beyond $n$80 in the Assembly Calculus Brainstack, weight perturbation on every read in kT-RAM, catastrophic ungated stack accumulation and RL-induced corruption in continual LLM Brainstacks, and overwrite protection versus reconsolidation in ZenBrain. Third, each uses some mechanism to make composition productive rather than destructive: Hebbian strengthening of assembly chains, AHaH self-regulation with anti-Hebbian/Hebbian cycles, null-space projection with routed stack loading, or sleep, PriorityMap, and StabilityProtector.

The non-equivalences are as important as the commonalities. “Zero forgetting” in the continual LLM work is qualified by routing conditions and by the distinction between weight drift and interference from ungated magnitude accumulation. The Assembly Calculus Brainstack is not an LLM adapter stack and does not aim at domain composition. Thermodynamic-RAM Brainstacks are implementation layers, not cognitive modules. ZenBrain’s Brainstack is a memory architecture whose empirical gains come from multi-layer routing, replay, and reconsolidation rather than from freezing additive parameter deltas. A plausible implication is that “Brainstack” has become a productive descriptor for systems that separate transient and persistent structure across levels, but the research content lies in the specific mechanisms—assemblies, memristors, MoE-LoRA routers, or layered memory stores—not in the label alone.