Sum of Signed Powers of Two (SOPOT)

• SOPOT is a numerical representation method that approximates real coefficients as sparse sums of signed powers of two, ensuring controlled error and reduced hardware complexity.
• It employs algorithms like MPGBP, which iteratively allocate signed power terms to minimize mean-squared error in coefficient approximation.
• This approach replaces costly multiplications with shift and add/subtract operations, significantly reducing gate count and power consumption in FBMC filter bank designs.

The Sum of Signed Powers of Two (SOPOT) is a numerical representation scheme wherein any real-valued coefficient, typically constrained by magnitude, is approximated as a sparse sum of signed powers of two. Motivated by the requirements of multiplierless hardware implementations, particularly in polyphase networks for filter bank multicarrier (FBMC) systems, SOPOT enables the replacement of costly multiplication operations with efficient combinations of shift and add/subtract units. Recent work formalizes SOPOT representation and advances efficient algorithms for generating high-accuracy SOPOT approximations of coefficient vectors, greatly reducing hardware complexity without compromising signal processing quality (Coelho et al., 28 Jan 2026).

1. Formal Structure of the SOPOT Number System

In SOPOT, any real coefficient $x$ (with $|x| \leq 1$) is approximated by a sparse expansion:

$x \approx \sum_{i=1}^K s_i\,2^{e_i}$

where $s_i \in \{+1, -1\}$ encodes the sign and $e_i \in \mathbb{Z}$ is the integer bit-plane (exponent), subject to $e_i \geq -B_{\text{max}}$ for some maximum negative bit-plane depth $B_{\text{max}}$ (i.e., lowest shift precision). $K$ denotes the maximum number of nonzero signed-power-of-two (SPT) terms, and thus controls the wordlength.

Equivalently, with $$p = [2^0, 2^{-1}, \ldots, 2^{-B_{\text{max}}}]^{\top}$$ and a sparse ternary coefficient vector $c \in \{-1, 0, +1\}^{B_{\text{max}}+1}$, the approximation is written as $\hat{x} = p^{\top}c$. This formulation facilitates vectorized and blockwise hardware processing (Coelho et al., 28 Jan 2026).

2. MPGBP: Greedy Matching-Pursuit SOPOT Conversion

To efficiently convert high-precision floating-point vectors into SOPOT representations, the Matching Pursuit with Generalized Bit Planes (MPGBP) algorithm operates directly on coefficient vectors $v \in \mathbb{R}^N$ to yield an SOPOT matrix $C \in \{-1, 0, +1\}^{N \times (B_{\text{max}}+1)}$.

Algorithmic outline:

• Initialization: $r_0 \leftarrow v$, $\hat{y} \leftarrow 0$, total SPT count $M \leftarrow 0$, bit-depth $B \leftarrow 0$, block width $P = \lfloor\sqrt{N}\rfloor$.
• Iterative update:
  • Codeword search: Select the $P$ indices with maximum $|r_i|$.
  • Codeword update: Assign $c_{j_i}(p) = \text{sign}(r_i(p))$ for selected $p$; zeros elsewhere.
  • Bit depth selection: $$k_i \leftarrow \lceil -\log_2\left(\frac{4}{3P}\sum_{p \in I_P}|r_i(p)|\right) \rceil$$.
  • Update:
  • $\hat{y} \leftarrow \hat{y} + 2^{-k_i}c_{j_i}$

  $r_{i+1} \leftarrow r_i - 2^{-k_i}c_{j_i}$ - Bookkeeping: Update $M$, $B$, increment $i$.

• Termination: Loop until $M \geq M_{\text{max}}$, $B > B_{\text{max}}$, or $\|r_i\|_\infty$ falls below threshold.

This blockwise reduction jointly allocates SPTs to the largest-magnitude residuals, optimizing overall vector mean-squared error (MSE) and hardware efficiency (Coelho et al., 28 Jan 2026).

3. Quantitative Error Metrics

SOPOT approximations are evaluated using established signal fidelity metrics:

• Mean-Squared Error (MSE):

$$\text{MSE} = \frac{1}{N} \sum_{n=1}^N (v[n] - \hat{y}[n])^2$$

This assesses the average energy of coefficient deviations.

• Maximum Error ($\mathcal{L}_\infty$):

$$E_\infty = \|v - \hat{y}\|_\infty = \max_n |v[n] - \hat{y}[n]|$$

This quantifies the maximum pointwise approximation error.

In FBMC contexts, a derived "interference MSE" based on intersymbol/intercarrier interference is also relevant, but vector MSE remains the principal comparison metric across design methods (Coelho et al., 28 Jan 2026).

4. Implications for Hardware Complexity

SOPOT-based multiplierless implementations fundamentally alter datapath complexity in digital filters:

• Each coefficient $x$ represented with $K$ SPTs requires $K$ single-bit left shifts and $K-1$ add/subtract operations.
• For an $N$-tap polyphase filter, total resource usage per branch is approximately $N \cdot K$ shifters and $N \cdot (K-1)$ adders/subtractors.

This architecture eliminates multipliers, which are comparatively expensive in gate count and power. Shift registers and ripple-carry adders dominate the implementation, leveraging CMOS efficiencies. Approximation quality is finely tunable by adjusting $K$ and $B_{\text{max}}$ (Coelho et al., 28 Jan 2026).

5. Comparative Evaluation of Multiplierless Methods

The following table summarizes three principal multiplierless design strategies as described in recent work (Coelho et al., 28 Jan 2026):

Method	Core Strategy	Accuracy/Complexity Tradeoff
Canonical Signed Digit (CSD)	Scalar CSD after B-bit quantization; ≤1 nonzero per 2 bits	Lowest cost, ~20 dB higher MSE than MPGBP
Signed Digit Loading (SDL)	Greedy: allocate SPT to max-abs-residual, 1 at a time	~20 dB lower MSE than CSD, simple logic
MPGBP (Matching Pursuit)	Blockwise matching pursuit with bit planes (P taps)	Lowest MSE for fixed SPT, modest overhead

CSD is extremely low-cost but provides suboptimal allocation of SPTs, resulting in high mean-squared and out-of-band (OOB) error. SDL improves allocation and thus accuracy, while MPGBP performs blockwise residual minimization for further MSE and OOB leakage reduction at practically similar control logic complexity.

6. Practical Significance in Multicarrier Systems

Adoption of SOPOT and its advanced conversion strategies such as MPGBP enable high-accuracy, multiplierless approximations of polyphase filter coefficients, directly benefiting FBMC/OQAM systems. These techniques ensure maintenance of low out-of-band emissions and bit error rates, prerequisites for modern wireless standards, while substantially reducing arithmetic and area complexity—favorable for energy- and area-constrained deployments (Coelho et al., 28 Jan 2026).