CSPADE: Complex Sparsity-Adaptive Equalizer

• CSPADE is a complex sparsity-adaptive equalizer that exploits sparse wireless channels, such as sparse multipath and mmWave massive MIMO, to achieve energy-efficient signal processing.
• It employs sparsity-inducing optimization with fractional-norm regularization and threshold-based logic to prune insignificant channel coefficients while preserving performance.
• VLSI implementations like AT-CSPADE and MAC-CSPADE demonstrate significant power reductions, achieving up to 66% energy savings compared to conventional equalizers.

The Complex Sparsity-Adaptive Equalizer (CSPADE) is a class of blind and data-aided signal processing algorithms, as well as their VLSI/ASIC implementations, designed to exploit sparsity in wireless communication channels, particularly in high-dimensional scenarios such as sparse multipath channels and millimeter-wave (mmWave) massive MIMO systems. CSPADE combines sparsity-inducing optimization principles with threshold-adaptive hardware logic to achieve low-complexity, energy-efficient equalization without significant loss in detection performance.

1. Algorithmic Foundations and Signal Modeling

CSPADE algorithms are predicated on the observation that physical propagation environments—either in delay (for delay-sparse ISI channels) or spatial/beamspace (for mmWave and arrays)—admit strongly sparse representations. The generic uplink model in massive MU-MIMO is

$\bar{y} = \bar{H} x + \bar{n}$

where $\bar{H} \in \mathbb{C}^{B \times U}$ is the antenna-domain channel, $x \in \mathbb{C}^U$ the user symbol vector, and $\bar{n}$ complex Gaussian noise. Beamspace processing applies a unitary spatial DFT, $F_B$, to map $\bar{y}$ to $y = F_B \bar{y}$, $H = F_B \bar{H}$. In mmWave, $H$ (the beamspace channel) is row-sparse due to limited scattering.

For blind sparse equalization (ISI context), with a complex equalizer $w \in \mathbb{C}^N$, the goal is to recover a constant modulus symbol stream from observations $y(n)=w^\mathrm{H} x(n)$ when $w$ should be sparse. In all models, the key is leveraging sparsity—imposing $\ell_p$ penalties or threshold-based computational skipping wherever a structural prior or empirical channel statistics permit.

2. Algorithmic Details: Cost Functions, Updates, and Threshold Policies

2.1 Fractional-Norm Regularized Blind Equalization

In constant modulus adaptive blind equalization, the cost function with a sparsity-inducing regularizer is

$$J(w) = \mathbb{E}\left[ (|y(n)|^2 - R)^2 \right] + \lambda \|w\|_p^p$$

where $\|w\|_p^p = \sum_{i=1}^N |w_i|^p$, $0<p\leq1$. The update employs a geodesic projection: $$w_{k+1} = w_k - \mu \left[ g_k - \left( \frac{|b_k^\mathrm{H} g_k|}{\|b_k\|^2} \right) b_k \right]$$ with $g_k$ the gradient of the constant modulus error and $b_k$ the fractional-norm gradient. This update maintains approximately constant $\ell_p$-norm and aggressively attracts small coefficients to zero (Abrar, 2017).

2.2 Threshold-Based Multiply Skipping for Beamspace LMMSE

For data-aided detection in mmWave beamspace MIMO, CSPADE exploits the observation that entries in the LMMSE equalizer matrix $W$ and the received vector $y$ are often simultaneously small. In the inner product

$\hat{s}_u = \sum_{b=1}^B W_{u,b} y_b$

the product $W_{u,b} y_b$ is omitted if both $|W_{u,b}|_{~\infty}$ and $|y_b|_{~\infty}$ are below set thresholds ($|x|_{~\infty} := \max\{| \Re x |, |\Im x|\}$), controlled by $(\tau_w, \tau_y)$. The resulting multiply-activity-rate, $\alpha$, directly reduces compute and dynamic power in hardware (Mirfarshbafan et al., 9 Jul 2024, Mirfarshbafan et al., 13 Nov 2025).

3. VLSI Architectures and Implementation

CSPADE is distinguished by hardware-aware algorithmic design. Two principal architectures are reported for VLSI:

• Adder-Tree CSPADE (AT-CSPADE): U dot-product pipelines, each with B complex multiplier units equipped with compare-and-mute logic per real multiplication. Skipped multiplications are replaced by zeros using a multiplexer.
• MAC-Based CSPADE (MAC-CSPADE): U complex MAC units, sequentially computing dot products over B cycles. If the threshold condition fails, both multiplier and accumulator are frozen for that cycle.

The threshold logic (comparator and clock-gate per multiplier) incurs area overhead (e.g., 15%) but with substantial dynamic power reductions when multiplier-activity rates are low (typ. $\alpha < 0.5$ in sparse channels).

4. Performance Analysis and Trade-Offs

CSPADE achieves substantial energy and power savings with negligible impact on SNR or BER. Selecting $(\tau_w, \tau_y)$ is performed off-line via Monte Carlo simulations to satisfy constraints (e.g., SNR penalty < 0.7 dB at 1% BER). The skipping mechanism introduces a bounded error, with SNR loss analytically related to the expected power of omitted products: $$\Delta \mathrm{SNR} \approx 10 \log_{10}\left(1 + \frac{\mathbb{E}[|e|^2]}{N_0}\right)$$ where $e$ is the total error from skipped multiplications (Mirfarshbafan et al., 9 Jul 2024, Mirfarshbafan et al., 13 Nov 2025). In blind ISI equalization, the $\ell_p$ parameter ($0<p\leq1$) and penalty weight $\lambda$ control sparsity and convergence: lower $p$ leads to greater sparsity, while larger $\lambda$ accelerates pruning but may degrade convergence if excessive (Abrar, 2017).

Measured Performance (22 nm FDSOI, B=64, U=8 or 16)

Implementation	Area (mm²)	f_clk (GHz)	Throughput (Gb/s)	Power (mW)	pJ/bit	Power Reduction vs ALMMSE
AT-ALMMSE	0.40	1	32	500	15.6	–
AT-CSPADE	0.50	1	32	229	7.2	54%
MAC-ALMMSE	0.006	1	0.128	$P_0$	–	–
MAC-CSPADE	0.0079	1	0.128	0.34$P_0$	–	66%

CSPADE achieves up to 54% (AT) and 66% (MAC) power savings compared to non-sparsity-adaptive beamspace equalizers, with energy efficiency as low as 7.2 pJ/bit (Mirfarshbafan et al., 13 Nov 2025). Measured SNR degradation is <0.5–0.7 dB for typical MMIMO LoS/NLoS channels.

5. Role of Sparsity, Thresholds, and Channel Statistics

The effectiveness of CSPADE depends fundamentally on the degree of channel sparsity. In mmWave environments where multipath and beamspace signatures are naturally sparse, significant activity reduction is observed. For denser, richly scattered channels, multiplier-skipping rates drop, reducing the achievable power savings—thresholds should be re-tuned or adaptively set per channel statistics to maintain optimal trade-offs.

In ISI channel equalization, balancing $p$ and $\lambda$ adapts the algorithm to the actual channel sparsity encountered; typical values $p \in [0.5, 0.8]$ achieve aggressive zero-attraction without excessive bias on significant taps.

6. Comparative Evaluation and Limitations

Comparative silicon results indicate that CSPADE-based designs outperform classical and proportionate LMMSE architectures both in dynamic energy consumption and normalized area efficiency. For 16-QAM, 22 nm FDSOI, CSPADE shows 11.8–12 pJ/bit (AT) at throughputs up to 46 Gbps (Mirfarshbafan et al., 9 Jul 2024, Mirfarshbafan et al., 13 Nov 2025), significantly outstripping previously reported ASICs (e.g., Castañeda et al., 12.6 pJ/bit, Liu et al., 36.1 pJ/bit). However, additional threshold logic incurs some area and standby leakage—projected at ~15% cost—which is amortized only when >25% of multiplies can be skipped.

A plausible implication is that CSPADE's benefit is maximized in channels and system regimes where empirical channel representations are highly compressible and hardware energy/delay constraints dominate.

7. Summary and Outlook

CSPADE unifies algorithmic and architectural sparsity exploitation for adaptive equalization in high-dimensional, sparse-channel wireless systems. Its mathematical formulation generalizes from nonconvex fractional-norm regularization for blind ISI equalization (Abrar, 2017) to threshold-adaptive dot-product muting in beamspace MMIMO LMMSE (Mirfarshbafan et al., 9 Jul 2024, Mirfarshbafan et al., 13 Nov 2025). The VLSI realizations illustrate substantial reductions in baseband power—a critical metric for large-scale MMIMO deployments—while maintaining near-optimal error-rate performance. Sustained benefit hinges on the preservation of beamspace sparsity, the fidelity of threshold setting, and the tight coupling between algorithmic and hardware design. Further research may explore on-line adaptivity of thresholds in varying propagation conditions and finer integration with tightly-quantized front ends.