Logarithmic Posit Arithmetic

• Logarithmic posit is a number representation that fuses posit scale encoding with logarithmic-domain computation, transforming multiplications into simpler additions.
• Variants like PLAM, LP, and EULER-ADAS tailor the approach to optimize hardware efficiency, precision, and energy consumption in DNN and accelerator designs.
• This design space leverages logarithmic reformulation to reduce computational complexity while maintaining competitive accuracy and improved error resilience.

Logarithmic posit denotes a family of arithmetic representations and datapaths that combine posit-style scale encoding with logarithmic-domain computation or logarithmic encoding of the significand. In the posit literature, the common starting point is a number of word length $N$ and exponent size $e_s$ with value $$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$, where $\mathrm{useed} = 2^{2^{e_s}}$; its logarithmic form is $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$. Different papers instantiate this idea differently: some approximate only the posit mantissa product through a logarithmic mapping, some introduce new logarithmic-posit encodings with parameterized bit fields, and some build bounded-regime SIMD engines that retain exact regime/exponent handling while moving mantissa multiplication into the log domain (Murillo et al., 2021, Ramachandran et al., 2024, Lokhande et al., 7 May 2026).

1. Posit structure and the logarithmic reformulation

A conventional posit separates sign, regime, exponent, and fraction. In hardware-oriented formulations, the regime is a run-length code, the exponent is an unsigned field of size $e_s$, and the fraction contributes an implicit leading $1$, so that the magnitude factorizes into a scale term and a mantissa term. This decomposition makes logarithmic reformulation natural because

$\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$

Under this view, multiplication can be recast as addition of logarithmic components, while sign is handled independently (Lokhande et al., 7 May 2026).

The same structural idea appears in the Posit Logarithm-Approximate Multiplier (PLAM), which writes

$$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$

then approximates the nonlinear term instead of implementing a full log/antilog datapath. The PLAM paper explicitly distinguishes this from a broader “Logarithmic Posit” concept in which one could perform true log-domain arithmetic over posits and reconstruct the triple $(k,e,f)$ from a logarithmic magnitude (Murillo et al., 2021).

A more radical reformulation is the Logarithmic Posit (LP) encoding used for DNN quantization. There, the standard posit exponent and fraction are replaced by a unified logarithmic fraction-exponent,

$e_s$0

and the decoded value becomes

$e_s$1

The LP family therefore preserves posit-style tapering through the regime while moving the significand into an explicitly logarithmic representation (Ramachandran et al., 2024).

2. Principal realizations in the literature

The literature does not define a single canonical logarithmic-posit format. Instead, it presents several distinct design points.

Approach	Core mechanism	Reported role
PLAM (Murillo et al., 2021)	Approximate $e_s$2 inside posit multiplication	Low-complexity posit multiplier for DNNs
LP / LPQ / LPA (Ramachandran et al., 2024)	Parameterized logarithmic-posit encoding with $e_s$3	Distribution-aware mixed-precision DNN inference
EULER-ADAS (Lokhande et al., 7 May 2026)	Bounded-regime posit plus logarithmic mantissa multiplication and shared quire	Energy-efficient ADAS neural compute engine

PLAM is the least disruptive variant. It keeps conventional posit decode and encode, adds the coarse scale terms exactly, and replaces the fraction multiplication by a fraction addition. For positive inputs $e_s$4 and $e_s$5, it uses

$e_s$6

followed by a threshold normalization: if $e_s$7, the reconstructed factor is $e_s$8; if $e_s$9, it is normalized as $$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$0, with the exponent incremented and the post-normalized fraction set to $$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$1. This eliminates the wide fraction multiplier and realizes the logarithmic step through adders, a comparator, and normalization logic rather than LUTs, CORDIC, or explicit exponentiation (Murillo et al., 2021).

EULER-ADAS retains exact posit regime/exponent scaling but applies iterative logarithmic multipliers (ILMs) only to the mantissa path. Its representation is a bounded-regime posit, $$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$2, where the regime count is limited so that $$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$3. The paper sets $$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$4 for Posit-$$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$5, $$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$6 for Posit-$$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$7, and $$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$8 for Posit-$$x = (-1)^s \cdot \mathrm{useed}^r \cdot 2^e \cdot (1+f)$$9. Multiplication is then expressed as exact addition of regime and exponent terms plus approximate addition of mantissa logs, followed by an efficient antilog. The six-stage pipeline comprises decode, stage-adaptive ILM mantissa multiplication with truncation, exact scale combination, SIMD-shared quire accumulation, rounding and normalization, and bounded-posit encoding (Lokhande et al., 7 May 2026).

LP departs further from standard posits by making the encoding itself distribution-aware. In LP, regime size $\mathrm{useed} = 2^{2^{e_s}}$0 controls tapering, exponent size $\mathrm{useed} = 2^{2^{e_s}}$1 controls dynamic range, and a continuous scale factor $\mathrm{useed} = 2^{2^{e_s}}$2 shifts where the representation concentrates its highest accuracy. The format is therefore intended არა simply as a logarithmic multiplier, but as a layer-wise tunable number system for quantized DNN inference (Ramachandran et al., 2024).

3. Arithmetic approximations, error models, and parameterization

PLAM uses the Mitchell-style approximation

$\mathrm{useed} = 2^{2^{e_s}}$3

This turns fraction multiplication into fraction addition. Its relative error depends only on the fractions: $\mathrm{useed} = 2^{2^{e_s}}$4 The maximum relative error is $\mathrm{useed} = 2^{2^{e_s}}$5, attained near $\mathrm{useed} = 2^{2^{e_s}}$6. The paper emphasizes that regime and exponent do not affect this bound, because the approximation is confined to the fraction path (Murillo et al., 2021).

EULER-ADAS adopts a more refined approximation hierarchy. For normalized mantissas $\mathrm{useed} = 2^{2^{e_s}}$7, the binary logarithm and antilog are iteratively refined over $\mathrm{useed} = 2^{2^{e_s}}$8 stages with relative error bound

$\mathrm{useed} = 2^{2^{e_s}}$9

With truncation retaining only $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$0 bits of the fractional term, the combined bound becomes

$\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$1

The precision modes are stage-adaptive: Posit-8 uses $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$2, $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$3; Posit-16 uses $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$4, $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$5; Posit-32 uses $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$6, $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$7. This establishes a direct accuracy–energy tuning interface through the pair $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$8 (Lokhande et al., 7 May 2026).

LP makes the parameterization itself part of the arithmetic design. Given $\ell(x)=r\cdot 2^{e_s}+e+\log_2(1+f)$9, encoding a nonzero $e_s$0 proceeds through

$e_s$1

followed by residual splitting into exponent and quantized logarithmic fraction. The paper gives the quantization and dequantization maps $e_s$2 and $e_s$3, and derives a local relative quantization error bound

$e_s$4

where $e_s$5 is the number of fraction bits in the unified logarithmic fraction-exponent. Because $e_s$6, $e_s$7, and $e_s$8 are all tunable, LP treats arithmetic accuracy as a distribution-matching problem rather than a fixed-format property (Ramachandran et al., 2024).

A recurring misconception is that logarithmic posit necessarily means fully exact log-domain posit arithmetic. The papers do not support that interpretation. PLAM is explicitly approximate in the fraction path, EULER-ADAS approximates only mantissa multiplication while keeping scale handling exact, and LP is a new encoding family rather than a transparent re-expression of standard posits (Murillo et al., 2021, Lokhande et al., 7 May 2026, Ramachandran et al., 2024).

4. Hardware architectures and application-specific accelerators

PLAM targets the posit multiplier as the most power-hungry unit in DNN architectures. Its decode stage uses leading-zero detection for regime run-length and polarity, extracts up to $e_s$9 exponent bits, adds exponents with carry cascading into the regime, adds fractions in fixed-point, performs threshold-based inverse-log reconstruction, then normalizes and rounds to nearest, ties to even. The implementation is combinational and was generated with FloPoCo; the reported benefit is removal of the fraction multiplier entirely (Murillo et al., 2021).

LPA, the accelerator accompanying LPQ, is a weight-stationary systolic array with native LP arithmetic. It uses boundary LP decoders and encoders, mixed-precision operating modes, and PEs that perform multiplication as addition of $1$0 and regime terms. Because addition in the log domain is expensive, the accumulation path converts logarithmic fractions to linear fractions for progressive accumulation, then converts back when packing outputs. The controller supports three per-layer modes: MODE-A with four 2-bit weights per PE, MODE-B with two 4-bit weights per PE, and MODE-C with one 8-bit weight per PE (Ramachandran et al., 2024).

EULER-ADAS is organized around SIMD unification. A single datapath supports $1$1Posit-8, $1$2Posit-16, or $1$3Posit-32 operation, with shared logic for regime/exponent scaling, ILM mantissa processing, and accumulation. Its accumulation path is a shared 128-bit quire for Posit-$1$4, Posit-$1$5, and Posit-$1$6, and its bounded-regime encoder/decoder shortens the critical path relative to variable-length regime encoding. The paper’s stated rationale is twofold: energy efficiency and reliability-aware ADAS acceleration (Lokhande et al., 7 May 2026).

These realizations also differ in where the logarithmic transform is placed. PLAM applies it inside the multiplier only. LP makes it part of the number representation. EULER-ADAS confines it to the mantissa multiply path while preserving a conventional posit-like scale decomposition. This suggests that “logarithmic posit” is best understood as a design space rather than a single microarchitectural template.

5. Accuracy, efficiency, and reliability trade-offs

PLAM reports that, versus state-of-the-art exact posit multipliers, the proposed technique reduces the area, power, and delay of hardware multipliers up to $1$7, $1$8, and $1$9, respectively, without accuracy degradation. In $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$0-bit DNN inference, the paper reports essentially the same inference accuracy as exact posit multiplication across ISOLET, UCI HAR, MNIST, SVHN, and CIFAR-10 workloads (Murillo et al., 2021).

LPQ and LPA report on average $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$1 drop in top-1 accuracy across various CNN and ViT models. Under identical $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$2, $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$3 systolic array configurations with $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$4 on-chip buffer, LPA achieves compute density $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$5, compared with $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$6 for ANT, $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$7 for BitFusion, and $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$8 for AdaptivFloat. The co-design is reported to achieve nearly $\log_2|x| = r\cdot 2^{e_s} + e + \log_2(1+f).$9 performance per area and $$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$0 energy efficiency relative to state-of-the-art quantization accelerators using different data types (Ramachandran et al., 2024).

EULER-ADAS reports FPGA reductions of LUT count by up to $$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$1, delay by up to $$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$2, and power by up to $$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$3 relative to exact posit neural compute engines, while achieving up to $$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$4 lower energy-delay product than radix-4 Booth-based posit multipliers. In $$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$5 CMOS, the bounded variants occupy $$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$6–$$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$7, consume $$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$8–$$\log_2|x| = k\cdot 2^{\mathrm{es}} + e + \log_2(1+f),$$9, and operate at up to $(k,e,f)$0. Application-level evaluation reports that the evaluated Posit-16 and Posit-32 configurations remain within about $(k,e,f)$1 percentage points of FP32 accuracy, and a TinyYOLOv3 prototype on Pynq-Z2 achieves $(k,e,f)$2 latency at $(k,e,f)$3 and $(k,e,f)$4 (Lokhande et al., 7 May 2026).

Reliability enters the logarithmic-posit literature most explicitly through bounded-regime designs. EULER-ADAS argues that standard variable-length regime encoding makes regime-field bit flips disproportionately impactful because magnitude is dominated by $(k,e,f)$5. Bounding $(k,e,f)$6 limits the maximum scale and the number of run and terminating bits. Its Expected Catastrophic Error model,

$(k,e,f)$7

is monotone in $(k,e,f)$8, and the paper states that bounded posit improves soft-error resilience by up to $(k,e,f)$9 in cited prior study (Lokhande et al., 7 May 2026).

6. Relation to log-space computing, competing formats, and terminological scope

The computational-statistics literature provides a useful contrast. One recent study compares posit, binary64, and logarithm representations for statistical kernels that manipulate extremely small probabilities. It reports that posit-based accelerators can achieve up to two orders of magnitude higher accuracy, up to $e_s$00 lower resource utilization, and up to $e_s$01 speedup, compared to log-space accelerators, with $e_s$02 performance per unit resource on FPGA. Its conclusion is not that log-space is obsolete, but that posit is often preferable when kernels mix multiplication and addition and would otherwise pay the cost of log-sum-exp (Xu et al., 13 Sep 2025).

That same study leaves room for hybrid use: a combined “logarithmic posit” approach is described as sensible only when an application’s dynamic range sometimes exceeds the chosen posit $e_s$03 or when rare numerical stabilizations are needed. This is a narrower claim than the hardware papers’ use of the term, but it highlights a central trade-off: logarithmic-domain arithmetic is attractive because multiplication becomes addition, yet expensive addition and conversion can dominate end-to-end systems unless the representation is carefully co-designed (Xu et al., 13 Sep 2025).

A sharper critique comes from takum arithmetic, a logarithmic tapered-precision number format introduced as a general-purpose alternative. Takum uses base $e_s$04, keeps an asymptotically constant dynamic range $e_s$05, and reports $e_s$06 exact inversion, higher exactness for multiplication, division, square root, and squaring, and higher encoding efficiency far from unity relative to posits. The takum paper therefore treats posit-style logarithmic schemes not as an endpoint, but as one point in a broader family of logarithmic tapered-precision arithmetic (Hunhold, 2024).

The phrase itself also has adjacent, non-equivalent uses. In stochastic numerical analysis, a “logarithmic Euler–Maruyama type scheme” preserves positivity by applying $e_s$07 to a positive SDE and mapping back by $e_s$08; that construction concerns positivity preservation, not posit number systems (Yi et al., 2020). In mathematical physics, perturbation theory for the logarithm of a positive operator concerns resolvent expansions, nested commutators, and contact terms for $e_s$09, again unrelated to posit arithmetic (Lashkari et al., 2018). A plausible implication is that “logarithmic posit” should be read contextually: within arithmetic and accelerator design it refers to posit-inspired logarithmic representations or logarithmic posit datapaths, whereas similar phrasing in other fields may involve only logarithms and positivity, not the posit number format.