In-Memory Single-FeFET XOR Scheme

• The paper introduces an in-memory single-FeFET XOR design that encodes XOR/XNOR operations within each bit, completely eliminating area overhead compared to conventional arrays.
• Utilizing ferroelectric polarization for threshold modulation, the scheme achieves up to 45× latency reduction over AES and twice the speed of prior FeFET XOR implementations.
• Experimental benchmarks demonstrate a 0% area overhead and >5× lower energy per bit than SRAM-CAM, promising scalable, energy-efficient in-memory compute architectures.

An In-Memory Single-FeFET XOR scheme utilizes the physical properties of ferroelectric field-effect transistors (FeFETs) to integrate XOR (exclusive OR) logic directly within memory cells. This approach enables area-efficient, low-energy, and high-throughput logic and encryption primitives, greatly enhancing data-intensive workloads in non-volatile memories and in-memory compute architectures. The principal innovation is mapping XOR/XNOR operations and, by extension, XOR-based encryption directly to a single FeFET device per bit—without the area or energy overhead of complementary circuits or multi-device cells inherent in conventional implementations (Zhao et al., 2023, Ovy et al., 3 Dec 2025).

1. Device Physics and Architectural Fundamentals

The single-FeFET XOR scheme is enabled by a FeFET whose threshold voltage ($V_t$) is programmed by the direction of its ferroelectric polarization ($P$). In state-of-the-art implementations, the FeFET consists of a ferroelectric layer (e.g., CuInP$_2$S$_6$ (CIPS), ~162 nm) integrated atop a semiconducting channel (e.g., MoTe$_2$, ~10 nm), with a thin high-$k$ dielectric (Al$_2$O$_3$, ~10 nm) and back gate (Zhao et al., 2023). Programming pulses ($\pm$5 V, ~4 $\mu$s) across top programming gates selectively set the local polarization as $P^+$ (n-type, $V_t$ shifted negative) or $P^-$ (p-type, $V_t$ shifted positive), which are non-volatile.

In the standard FeFET electrical model, the channel current is

$$I_{DS} \approx \mu \, C_{ox} \left(\frac{W}{L}\right) (V_{GS} - V_{th0} \mp Q_p/C_{ox})V_{DS} - \frac{1}{2} V_{DS}^2,$$

where $\mp Q_p/C_{ox}$ captures the threshold shift due to polarization charge $Q_p$. The device exhibits a hysteresis window in $V_t$ of approximately 3 V, permitting robust binary (and multi-level) storage and logic (Zhao et al., 2023).

2. Single-FeFET XOR Operation: Logical and Circuit Mapping

The XOR (or its complement XNOR) is implemented by bias mapping and sense line assignment:

• Inputs: The search bit (or plaintext/key) is applied to the gate; the stored bit (or ciphertext) is encoded in the FeFET's polarization state.
• Logic Levels: Logical '0' and '1' are assigned to different combinations of $V_{GS}$ and stored polarization.
  • For example, in XNOR ("match") mode: match (high $I_{DS}$) when $A=B$ (search bit equals stored bit), mismatch (low $I_{DS}$) otherwise; in XOR mode, mapping is inverted.
• Thresholding: Only matched input–memory pairs (i.e., correct $V_{GS}$ relative to $V_t$) produce channel current above threshold—other combinations remain subthreshold.

During in-memory encryption (Ovy et al., 3 Dec 2025), a single FeFET cell per bit stores the XOR of the plaintext and key, with:

• $C = P \oplus K$ encoded as $V_t = V_{t,L}$ (low) for $C=0$, and $V_t = V_{t,H}$ (high) for $C=1$.
• Decryption is performed by biasing bit-lines and source-lines based on the key and reading with an intermediate word-line voltage; the state of the source-line reveals $P = C \oplus K$ in a single cycle.

3. In-Memory CAM, Encryption, and Array Architectures

In the context of content-addressable memory (CAM), a 1-transistor-per-bit (1T) array leverages FeFET XOR/XNOR matching for word-level search:

• Each CAM cell is a single FeFET; the array is organized either as a series (NAND) for all-bits-match detection, or as parallel (NOR) for Hamming-distance measurement—the match line reflects the number of matched storage/search vector pairs (Zhao et al., 2023).

For encrypted memory (Ovy et al., 3 Dec 2025):

• Each FeFET cell directly stores an encrypted bit; unlike prior work (2-FeFET-per-bit cells), cell count and density match that of an unencrypted array.
• Array-level configuration allows for simultaneous encryption/decryption of all columns in a row using only a single read or write pulse, with column-wise BL/SL bias determined by the key.

The design supports efficient scaling to multi-megabit arrays, with careful segmentation, per-row calibration, and adaptive sense amplifiers to counter process variation and sneak path currents.

4. Performance Metrics and Comparative Analysis

Quantitative benchmarks demonstrate the efficiency of the in-memory single-FeFET XOR scheme in both CAM and encrypted memory domains:

Scheme	Area Overhead	Encryption Cycles	Decryption Cycles	Throughput (Enc./Dec., Mbps)
AES	+0.00309 mm²	115.5	121	28.32 / 28.32
Prior 2-FeFET XOR	100%	5	16	640 / 200
Single-FeFET XOR (1T)	0%	2.5	8	1280 / 400

• Area: Single-FeFET XOR achieves zero area overhead versus unencrypted arrays, 50% reduction over prior 2-FeFET solutions, and ~25$\times$ reduction over 10T SRAM-CAM (Zhao et al., 2023, Ovy et al., 3 Dec 2025).
• Latency: Encryption is completed in 2.5 cycles and decryption in 8 cycles per 128-bit row (at 25 MHz), over 45$\times$ faster than AES and twice as fast as prior FeFET XOR.
• Power/Energy: Dynamic power is minimal (fJ/bit writes, nW reads); read energy per bit is $\approx$0.3 pJ, $>5\times$ lower than SRAM-CAM.
• Application Impact: On CNN inference workloads, the scheme yields average latency reductions of 95% vs. AES and 50% vs. prior FeFET XOR, with no storage penalty (Ovy et al., 3 Dec 2025).

5. Technological Extensions: Multi-Level Cells and Hamming Distance

The FeFET-based architecture can be extended to multi-level cell (MLC) operation, allowing multiple bits to be encoded in quantized $V_t$ states:

• For 2-bit per cell storage, four $V_t$ levels ($V_{t,00}, V_{t,01}, V_{t,10}, V_{t,11}$) are mapped to the 2-bit ciphertext, with decryption exploiting thresholded word-line pulses in separate cycles (Ovy et al., 3 Dec 2025).

In CAM, NOR-array configurations use the analog match line discharge rate for direct Hamming distance measurement between input and stored words, supporting distance-based search and classification functions (Zhao et al., 2023).

6. Scaling Challenges and Proposed Solutions

Scaling the single-FeFET XOR scheme to large arrays introduces several challenges:

• Device Variation: Fluctuations in polarization charge ($Q_p$) and $V_t$ shifts induce match current dispersion, demanding per-row calibration and adaptive reference sensing.
• Sneak Paths: In NOR-style arrays, parasitic currents can degrade match accuracy, mitigated by match-line segmentation and local gating.
• Program Disturb: Adjacent cell programming disturb is addressed by local write buffers and write-verify schemes.
• Error Resilience: Extreme-scale arrays can incorporate error-correction codes or majority-voting per word.

Proposed architectural solutions include hierarchical match-line segmentation, adaptive sense amplifier reference tuning, and exploration of analog/multi-level FeFET states for high-density, analog in-memory compute (Zhao et al., 2023).

7. Impact and Application Domains

The in-memory single-FeFET XOR scheme constitutes a scalable building block for ultra-dense, energy-efficient, and high-throughput data-stream processing. It is applicable to:

• Content addressable memory for pattern matching, search, and Hamming-distance applications
• Secure, dense, and fast-encrypted non-volatile memory arrays
• Data-intensive acceleration in neural networks, image processing, and reconfigurable circuits

By leveraging the intrinsic XOR/XNOR functionality in the physical device, it eliminates cell count and access cycle penalties, providing an efficient hardware substrate for emerging in-memory compute and encryption workloads (Zhao et al., 2023, Ovy et al., 3 Dec 2025).