Single-Error 4:2 Compressor

• Single-Error 4:2 compressor is an approximate hardware unit that reduces four inputs with a bounded error magnitude of ±1 across multiple input patterns.
• It employs spin-wave logic with majority gates to simplify design, avoiding the need for a directional coupler and ensuring error bounds.
• The design trade-offs include lower energy consumption, reduced delay, and minimal device count compared to CMOS and reversible logic implementations.

A single-error 4:2 compressor is ordinarily understood, in the approximate-arithmetic sense reflected in the literature considered here, as a compressor whose deviation from the exact 4:2 truth table is singular, such as only one erroneous input pattern or one isolated output error event. None of the cited works presents that property directly. The closest relevant case is a directional-coupler-free spin-wave approximate 4:2 compressor whose arithmetic error magnitude is bounded to 1 but whose erroneous behavior spans multiple input combinations; it is therefore more accurately classified as a bounded-unit-error approximate 4:2 compressor than as a true single-error compressor (Mahmoud et al., 2021). Exact baselines for comparison exist in reversible logic and exact spin-wave logic, while FPGA-oriented work treats the 4:2 compressor mainly as one primitive within a broader compressor-tree and generalized-parallel-counter design space (Misra et al., 2015, Mahmoud et al., 2021, Rasoulinezhad et al., 2020).

1. Terminological scope and common misclassification

The central distinction is between single occurrence of error and unit magnitude of error. The spin-wave approximate compressor most closely associated with this topic makes errors on multiple truth-table rows, yet every erroneous arithmetic result differs from the exact value by only $\pm 1$ (Mahmoud et al., 2021). This means that bounded error magnitude does not imply a single-error property.

That distinction matters because approximate 4:2 compressors are often described using several incompatible viewpoints: output-bit error frequency, arithmetic row error, and error-distance bounds. In the cited spin-wave work, the reported “average error rate” is based on output-bit behavior, whereas the arithmetic-compressor interpretation obtained from the full truth table yields a different count of erroneous rows. A compressor can therefore have $ED_{max}=1$ and still be far from “single-error” in the usual taxonomy.

Within this literature, the most precise characterization of the relevant approximate design is: exact $C_{o1}$, approximated $(S,C_{o2})$, multiple erroneous input combinations, and maximum arithmetic error distance 1. That profile is technically important, but it is not equivalent to a true single-error truth-table deviation.

2. Exact 4:2 compression and signal conventions

The exact 4:2 compressor baseline is presented in the literature as a two-stage reduction of four primary inputs plus carry-in. In the conventional organization recalled for the approximate spin-wave work, the accurate 4:2 compressor is built as two cascaded full adders, producing an intermediate transport $C_{o1}$ and final outputs $S$ and $C_{o2}$, with the weighted equality

$$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$

This is the reference arithmetic relation against which approximation is assessed in that work (Mahmoud et al., 2021).

The reversible-logic implementation provides an exact gate-level decomposition of the same basic two-stage structure. It computes

$S_1 = I_1 \oplus I_2 \oplus I_3,$

$C_1 = I_1 I_2 + I_2 I_3 + I_1 I_3,$

$ED_{max}=1$0

$ED_{max}=1$1

so that

$ED_{max}=1$2

This realization is exact and is used primarily as a reversible baseline rather than as an approximate or error-bounded compressor (Misra et al., 2015).

An exact spin-wave implementation adopts a different signal convention. It defines

$ED_{max}=1$3

$ED_{max}=1$4

$ED_{max}=1$5

and the encoded arithmetic relation becomes

$ED_{max}=1$6

This indicates that carry naming and weighting are not uniform across papers, even when all of them describe a “4:2 compressor” (Mahmoud et al., 2021). A consequence is that any claim of “single-error” must be interpreted with respect to a specific output convention and weighting rule.

3. Directional-coupler-free approximate spin-wave realization

The approximate spin-wave compressor that is most relevant to this topic is built directly from one 3-input majority gate and one 5-input majority gate, without a directional coupler (Mahmoud et al., 2021). The stated logic is slightly notationally inconsistent in the source text, but the truth table and operation description support the intended mapping

$ED_{max}=1$7

$ED_{max}=1$8

$ED_{max}=1$9

Using majority notation,

$C_{o1}$0

and

$C_{o1}$1

Hence

$C_{o1}$2

$C_{o1}$3

The architectural simplification is explicit: the exact two-output relation $C_{o1}$4 is collapsed into a complementary pair derived from a single 5-input majority decision. That reduction in logic complexity is the source of approximation. It also removes the need for the directional coupler that had previously been required when approximate spin-wave full adders were cascaded directly, because a direct cascade produced output amplitudes dependent on the input pattern. Reformulating the compressor in majority logic avoids that normalization stage.

The signal flow has two distinct paths. In the $C_{o1}$5 path, $C_{o1}$6 and $C_{o1}$7 interfere first, their result then interferes with $C_{o1}$8, and $C_{o1}$9 is read by phase detection; this output is exact. In the $(S,C_{o2})$0 path, $(S,C_{o2})$1 and $(S,C_{o2})$2 interfere first, that result interferes with $(S,C_{o2})$3 and $(S,C_{o2})$4 with geometrically engineered inversion for the latter two, then the resulting wave interferes with $(S,C_{o2})$5; $(S,C_{o2})$6 and $(S,C_{o2})$7 are extracted by threshold detection from the same analog spin-wave result.

4. Error structure and the absence of a true single-error property

For the proposed approximate compressor without directional coupler, the full truth table yields 11 erroneous input combinations out of 32, ordered as $(S,C_{o2})$8:

$(S,C_{o2})$9

The arithmetic value represented by the approximation is

$C_{o1}$0

and the per-input error distance is

$C_{o1}$1

For every erroneous case, the arithmetic error distance has magnitude exactly 1; there are no cases with $C_{o1}$2 (Mahmoud et al., 2021).

This bounded behavior is what makes the design relevant to studies of single-error compressors, but it does not make the design itself single-error. The reconstructed arithmetic metrics are:

$C_{o1}$3

$C_{o1}$4

$C_{o1}$5

$C_{o1}$6

$C_{o1}$7

and, if normalized by the maximum exact sum 5,

$C_{o1}$8

These formulas are not introduced explicitly in the paper; they are reconstructed from the truth table and arithmetic function.

The same source reports a different set of error figures based on output-bit behavior: $C_{o1}$9 for $S$0, $S$1 for $S$2, and an overall value reported as $S$3 in Table IV, while also stating that the design has the same “average error rate” as the with-directional-coupler version, namely $S$4 (Mahmoud et al., 2021). The inconsistency is internal to the source. Under arithmetic row counting, the design is wrong on $S$5 of cases. Under the paper’s bitwise accounting, the reported figures differ. The technically stable conclusion is that the compressor is multi-pattern bounded-error, not single-error.

5. Spin-wave physics, detection rules, and quantitative trade-offs

The physical implementation relies on thresholding the normalized magnetization produced by spin-wave interference (Mahmoud et al., 2021). For $S$6, with threshold $S$7, the decision rule is: $S$8 if the resulting normalized magnetization is $S$9, else 0. For $C_{o2}$0, the threshold condition is flipped: $C_{o2}$1 if the normalized magnetization is $C_{o2}$2, else 1. Physically, the same interference result is therefore thresholded into complementary outputs, which is consistent with the logic relation $C_{o2}$3.

The waveguide-level majority behavior is constrained by three conditions: the waveguide width must satisfy $C_{o2}$4, all waves must be excited with the same amplitude, wavelength, and frequency, and distances must be chosen as integer or half-integer multiples of $C_{o2}$5 depending on whether constructive interference is intended for in-phase or out-of-phase inputs. The geometric rules are

$C_{o2}$6

for constructive interference of in-phase waves, and

$C_{o2}$7

for constructive interference of out-of-phase waves. The simulation setup uses $C_{o2}$8 at $C_{o2}$9, with explicit distances such as

$$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$0

The reported hardware trade-offs for the approximate compressor, its exact spin-wave counterpart, and several alternative technologies are summarized below. The error-rate entries are the values reported in the source table and do not resolve the paper’s internal inconsistency between bitwise and arithmetic-row error counting.

Design	Reported figures	Comparison note
Accurate SW compressor	error rate 0; energy 0.2 fJ; delay 6.56 ns; devices 14	Exact spin-wave baseline
Approximate SW with DC	error rate 0.31; energy 0.137 fJ; delay 11.4 ns; devices 8	Earlier approximate SW form
Approximate SW without DC	error rate 0.31; energy 0.137 fJ; delay 3.4 ns; devices 8	Proposed design
CMOS1	error rate 0.125; energy 0.172 fJ; delay 0.049 ns; devices 40	Lower reported error, higher energy
CMOS2	error rate 0.375; energy 0.16 fJ; delay 0.048 ns; devices 28	Higher reported error
Spin-CMOS1	error rate 0.31; energy 173 fJ; delay 3 ns; devices 28	Same reported error, far higher energy
Spin-CMOS2	error rate 0.25; energy 338 fJ; delay 4 ns; devices 42	Higher energy and device count

From these values, the claimed trade-offs are specific: versus the accurate spin-wave compressor, the proposed design uses 31.5\% less energy and is 1.93× faster; versus the approximate spin-wave compressor with directional coupler, it has the same energy and error rate but 3× lower delay; versus CMOS2, it uses 14\% less energy and has 17\% lower error rate; versus Spin-CMOS1, it provides the same error rate with about 3 orders of magnitude lower energy; and it has the smallest device count among the listed designs (Mahmoud et al., 2021).

6. Exact baselines and broader implementation contexts

The exact spin-wave 4:2 compressor serves as a direct reference point for any single-error or bounded-error proposal. It consists of 4 XOR gates and 2 Majority gates, is validated by micromagnetic simulation in MuMax3, and is realized in $$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$1 waveguides of width $$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$2 and thickness $$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$3 at $$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$4 with $$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$5. Its reported figures are 0.16 fJ energy, 4.68 ns delay, and 11 devices, with exact functionality over all 32 input patterns (Mahmoud et al., 2021). For approximate-compressor research, this is an exact spin-wave baseline rather than a single-error construction.

The reversible-logic baseline is exact in a different implementation domain. It uses two Inventive0 gates, two constant inputs, four garbage outputs, and has

$$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$6

The same work also states

$$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$7

where $$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$8 counts 2-input XOR gates, $$I_1 + I_2 + I_3 + I_4 + C_{in} = S + 2C_{o1} + 2C_{o2}.$$9 counts 2-input AND gates, and $S_1 = I_1 \oplus I_2 \oplus I_3,$0 counts NOT gates. This design is relevant as an exact reference architecture for reversible implementations, not as an approximate or single-error compressor (Misra et al., 2015).

In FPGA architecture research, the 4:2 compressor is treated as a canonical carry-save primitive, but not as the preferred abstraction in every mapping flow. LUXOR adds a dedicated 6-input XOR gate in parallel with the normal LUT datapath, while X-LUXOR+ and I-LUXOR+ add vendor-specific enhancements. The reported silicon area overhead is less than 0.5\% for LUXOR and 5–6\% for LUXOR+, with delay increments of 1–6\% and 3–9\%, respectively. On micro-benchmarks, LUXOR yields an average reduction of 13–19\% in logic utilization, and BNN benchmarks show an average reduction of 37–47\% (Rasoulinezhad et al., 2020). That work explicitly discusses the 4:2 compressor, but its main point is that FPGA compressor trees are often better expressed with generalized parallel counters such as C6:111 and C25:121 than with repeated explicit C4:2 blocks. It is therefore relevant to implementation methodology, not to the error taxonomy of single-error compressors.

Taken together, these works establish a clear technical boundary. Exact 4:2 compressors are well characterized in reversible logic and spin-wave logic, and compressor trees are well studied in FPGA architecture. The approximate spin-wave compressor most closely associated with the “single-error” question is not actually a true single-error design. Its defining property is not singular error occurrence, but bounded unit-magnitude arithmetic error across multiple input patterns.