SimCortex: Cortex Simulation & Reconstruction

• SimCortex is a recurring label for cortex-oriented systems that include distributed neural simulation, FPGA neuromorphic emulation, and MRI-based cortical surface reconstruction.
• The frameworks employ distinct methodologies such as master–worker network architecture, hierarchical connectivity, and time multiplexing for real-time simulation.
• SimCortex systems advance brain research by enabling scalable neural modeling and precise neuroanatomical reconstruction with strict topology preservation.

SimCortex is a label applied to multiple cortex-oriented research systems spanning distributed neural simulation, neuromorphic FPGA emulation, and cortical surface reconstruction from MRI. In one usage, it denotes an early proposal for a distributed cortex simulation system built from loosely coupled software “neurons” communicating over LAN, WAN, or grid-style environments in a master–worker architecture (Tomas, 2014). In another, it denotes a massively parallel FPGA-based cortex simulator organized around minicolumns and hypercolumns for real-time simulation of large structurally connected spiking neural networks (Wang et al., 2018). More recently, the same name has been used for a deep learning framework that simultaneously reconstructs left and right white-matter and pial cortical surfaces from T1-weighted MRI while preserving topology and minimizing collisions (Moradkhani et al., 9 Jul 2025). This suggests that “SimCortex” functions less as a single canonical system name than as a recurring label for technically distinct cortex-related frameworks.

1. Nomenclature and scope

Within the literature considered here, the name SimCortex refers to at least three different research objects: a high-level distributed simulation proposal, a hardware neuromorphic simulator, and a cortical-surface reconstruction framework. Their overlap is conceptual rather than implementation-level: each uses cortical organization as its organizing principle, but the target problems, substrates, and evaluation criteria differ substantially.

Usage of “SimCortex”	Problem domain	Core formulation
Distributed cortex simulator proposal	Distributed computer network environments	Loosely coupled software “neurons,” master–worker coordination, event-message passing
FPGA neuromorphic cortex simulator	Large-scale spiking neural network simulation	Minicolumns, hypercolumns, hierarchical communication, time multiplexing
Collision-free cortical surface reconstruction	MRI-based neuroanatomical modeling	Nine-class segmentation, collision-free initialization, multiscale diffeomorphic deformation

A related but differently named system is Simple Cortex (SC), which belongs to the cortical-inspired machine intelligence literature rather than the SimCortex nomenclature. SC is presented as a model of cells in the sensory nervous system, with binary stimuli, permanence-based synapses, dendritic thresholds, inhibition, boosting, and online learning on CPU/GPU hardware (Giorgio, 2017).

2. Distributed network SimCortex as a research proposal

The 2014 SimCortex proposal defines a distributed cortex-style simulator as a collection of loosely coupled software “neurons” communicating over a network. Each node embodies a simplified artificial neuron augmented with selected biological features such as plasticity. The system is organized as a master–worker pattern: master node(s) coordinate experiments, distribute parameters, and collect global statistics, while worker nodes host one or more neuron processes and manage local membrane states, synaptic queues, and communication buffers (Tomas, 2014).

The proposal assumes deployment across LAN, WAN, or grid-style environments, including volunteer computers à la SETI@home. Nodes communicate via a custom lightweight protocol layered just above UDP/TCP, with the stated goal of “as low-level an implementation as possible on the ISO/OSI stack,” although no packet format is specified. Logical connectivity may be fully connected in principle, with actual synaptic links instantiated at runtime according to a sparse connectivity graph. The data flow is explicitly staged: the master broadcasts the global simulation time-step and configuration updates; each worker integrates its assigned neurons for the current $\Delta t$ and generates spike-events; spike-events are packaged into small network messages and routed to target worker(s); workers receive incoming spikes and enqueue them for synaptic processing in the next time-step; workers periodically send summary statistics such as firing counts and average synaptic weights back to the master.

The simulation engine is described as a time-driven, synchronous update scheme with event-message passing. The per-worker loop waits for a start-step broadcast, integrates local neurons over $\Delta t$, packages $(\text{neuron\_id}, \text{timestamp})$ spike messages, receives and enqueues peer messages, updates synaptic states and plasticity, and reports step completion and local statistics. Work is partitioned by assigning groups of neurons to each worker, and dynamic re-partitioning is suggested if communication overhead grows too large, but no load-balancing formula is given.

Biologically, the proposal explicitly rejects full Hodgkin–Huxley chemistry and instead emphasizes temporal coding of spikes, neuroplasticity rules, and selective biological features only where they most affect network-level intelligence emergence. No explicit differential equations are committed to, and the paper reports no packet formats, pseudocode, benchmarks, or scaling results. Applications are framed as exploratory research into how minimal biological features such as plasticity and temporal coding can give rise to swarm-style intelligence or rudimentary consciousness, as well as a test-bed for cognitive-science hypotheses about forgetting, pruning, and network-level reorganization. The principal limitations are likewise explicit: full biological realism is deemed too costly, scalability is constrained by network bandwidth and unspecified load balancing, and the system remains a roadmap rather than a finished implementation.

3. FPGA SimCortex: structural abstraction and communication hierarchy

The 2018 FPGA-based SimCortex takes a different approach by abstracting cortical organization into minicolumns and hypercolumns. In this formulation, a minicolumn is the basic building block and contains up to 100 neurons in up to eight configurable types, while a hypercolumn is a functional block containing up to 128 minicolumns (Wang et al., 2018). This abstraction is motivated by the need to avoid prohibitively large point-to-point connectivity tables in large-scale fully connected spiking models.

The hardware decomposition centers on a single neural engine per FPGA with three pipelined arrays. The minicolumn array implements time-multiplexed minicolumns and generates spike counts. The axon array implements programmable axonal delays via a TX/RX two-phase DDR scheme. The synapse array modulates events by synaptic weights and maps them to destination minicolumns. A parameter LUT, built from on-chip CAM and small SRAMs, stores neuron, hypercolumn, and connection parameters, while a master controller manages global timing, memory arbitration, and I/O.

Connectivity is encoded hierarchically rather than point-to-point. The parameter LUT uses a parallel CAM of $512 \times 27$ bits, implemented in flip-flops, to store 27-bit thresholds defining address ranges and return an index in 3 cycles. Indexed buffers in on-chip SRAM then provide access to neuron-type parameters, hypercolumn connection parameters such as axonal delays and offset ranges, and synapse connection data including pre-connection information and neuron-connection masks. Event addresses are 27 bits wide and partitioned into a 20-bit hypercolumn address concatenated with a 7-bit minicolumn address.

Communication is also hierarchical. Connectivity is specified at the hypercolumn level, then refined at the minicolumn level, and finally at the neuron-type level using $8 \times 8$ masks. Event routing uses 16 axonal ports with programmable delays from 1 ms to 16 ms. Under this scheme, one source minicolumn can reach up to 16 hypercolumns $\times 128$ minicolumns $\times 100$ neurons, approximately 200 000 targets. The axon array demultiplexes events into 16 Delay_FIFO structures and writes them into two DDR banks according to odd or even delays, while stochastic read-out approximates the desired delay distribution. In the synapse array, 16 parallel arbiters each manage 64 k time-multiplexed minicolumns, using fast CAM lookup and a bypass mechanism when consecutive events share the same hypercolumn.

4. Neuron dynamics, implementation substrate, and measured scaling

The FPGA SimCortex implements a stochastic conductance-based leaky-integrate-and-fire model using fixed-point arithmetic and LFSR noise. Its neuron datapath consists of a single PSC generator followed by a soma in an 11-stage pipeline, allowing throughput of one neuron per clock (Wang et al., 2018). The soma has active and refractory states: in the active state it integrates PSC input and emits a spike if the membrane potential overflows beyond threshold; in the refractory state it ignores inputs for $U_{\mathrm{rfc}}$ ms and then resets after spiking.

Several hardware optimizations are central to the design. Stochastic LIFs store only the MSBs of state variables and generate LSB noise on the fly, yielding a 4× memory reduction together with biologically realistic variability. The synapse array is a 12-stage pipeline that processes up to 32 connections per cycle in four-cycle slots. Time multiplexing uses a burst-size of 1 024 with ping-pong DDR bursts and a read-in-advance FIFO so that the time-multiplexed neuron state is available when needed. External memories are reserved for state and delayed events, while parameters and connection patterns remain in hierarchical CAM and on-chip SRAM.

The reported implementation target is an Altera Stratix V 5SGXEA7N2F45C2 on a Terasic DE5 board with 234 720 ALMs, 52 Mb on-chip RAM, and 256 DSP blocks. Reported utilization is 157 978 ALMs (67%), 41 Mb RAM (78%), and all 256 DSPs. In real time at a 1 ms update interval, 176 k time-multiplexed minicolumns correspond to 20 M simulated neurons. At a 5 ms update interval, 1 M time-multiplexed minicolumns correspond to 100 M simulated neurons. With dynamic assignment and activity not exceeding 0.7%, the design reports support for up to 2.6 billion neurons on one board. Verification is performed by emulating a simplified auditory cortex with 100 million neurons.

Power and throughput are reported explicitly. Total board power is approximately 32.4 W, which at 20 M neurons and 1 ms real-time corresponds to 1.62 $\mu$W per neuron. The design therefore presents SimCortex not merely as a simulation concept but as a quantitatively characterized neuromorphic platform for real-time, structurally connected spiking networks.

5. SimCortex for simultaneous cortical surface reconstruction

A distinct 2025 SimCortex framework targets cortical surface reconstruction rather than spiking simulation. Its objective is to reconstruct the inner white-matter and outer pial boundaries of both hemispheres from a single T1-weighted MRI volume with both high geometric fidelity and strict topology preservation: each surface must remain a genus-0 2-sphere, free of self-intersections, and surfaces across hemispheres must not overlap (Moradkhani et al., 9 Jul 2025).

The pipeline contains three stages: MRI preprocessing, segmentation-based initialization, and multiscale diffeomorphic deformation. The first stage uses a 3D U-Net with encoder channels $$[1 \rightarrow 16 \rightarrow 32 \rightarrow 64 \rightarrow 128 \rightarrow 128]$$ and decoder channels $\Delta t$0, with LeakyReLU activations, trilinear upsampling, and skip connections, on $\Delta t$1 input volumes normalized to $\Delta t$2. The output is a nine-class tissue label map corresponding to background, left/right white matter, cortical gray matter, amygdala-hippocampus complex, and lateral ventricles. Training uses voxel-wise categorical cross-entropy against FreeSurfer-derived labels with Adam at learning rate $\Delta t$3 and batch size 10.

From this segmentation, SimCortex constructs four subject-specific spherical template meshes. The procedure begins with binary masking, then computes the signed distance field of the largest connected component and Gaussian-smooths it with $\Delta t$4 mm. A fast-marching topology-correction step uses

$\Delta t$5

with guaranteed spherical topology. Marching Cubes is then applied at threshold $\Delta t$6, beginning with $\Delta t$7 for the pial mesh; if pairwise vertex/face collision checks detect contralateral collisions, $\Delta t$8 is decremented by 0.05 and extraction is repeated. The white-matter threshold is then set to $\Delta t$9, and the same process is repeated with decrements of 0.1 until the mesh is collision-free against all other surfaces. This yields four non-overlapping genus-0 meshes in MNI152 space.

Refinement is performed by multiscale diffeomorphic deformation driven by stationary velocity fields (SVFs). If $(\text{neuron\_id}, \text{timestamp})$0 is time-invariant, the deformation obeys

$(\text{neuron\_id}, \text{timestamp})$1

The final map is computed by scaling-and-squaring:

$(\text{neuron\_id}, \text{timestamp})$2

In practice, seven squaring steps are performed after dividing $(\text{neuron\_id}, \text{timestamp})$3 by $(\text{neuron\_id}, \text{timestamp})$4, with Gaussian smoothing at $(\text{neuron\_id}, \text{timestamp})$5 mm after each intermediate step. A second 3D U-Net with channels $(\text{neuron\_id}, \text{timestamp})$6 predicts $(\text{neuron\_id}, \text{timestamp})$7 SVFs at increasing resolution, and each diffeomorphism simultaneously deforms all four meshes:

$(\text{neuron\_id}, \text{timestamp})$8

Because each $(\text{neuron\_id}, \text{timestamp})$9 is diffeomorphic, intermediate surfaces remain genus-0 and do not acquire new self-intersections.

Training and evaluation are specified in detail. For segmentation, the HCP-OASIS split is 356 train, 102 validation, and 51 test, with CNP comprising 51 held-out subjects for generalization. The surface reconstruction network uses AdamW with learning rate $512 \times 27$0, weight decay $512 \times 27$1, batch size 5, and 250 epochs, requiring approximately 28 hours on two NVIDIA RTX A6000 GPUs. The mesh loss combines Chamfer distance, edge regularization, and normal consistency, with weights $512 \times 27$2, $512 \times 27$3, and $512 \times 27$4.

Quantitative results emphasize topology and runtime. On HCP-OASIS, the percentage of pial-L versus pial-R intersecting faces is 0.004% for SimCortex, compared with 0.268% for CorticalFlow++ and 0.188% for Vox2Cortex. On the independent CNP set, average metrics are Chamfer = 1.51 mm, ASSD = 0.41 mm, HD = 7.51 mm, and Self-Intersection Fraction = 0.13%. On HCP-OASIS, SimCortex yields average Chamfer = 1.11 mm, ASSD = 0.32 mm, HD = 6.86 mm, and SIF = 0.04%. Inference time is 0.28 s per subject for all four surfaces, versus 0.70 s for CorticalFlow++ and 0.77 s for Vox2Cortex. The reported limitations are also explicit: Chamfer and ASSD are marginally higher than CorticalFlow++ for white-matter surfaces, and reconstructed meshes can appear smoother with slightly shallower sulcal depth.

6. Relation to Simple Cortex and broader interpretation

Simple Cortex (SC) is not itself named SimCortex, but it occupies an adjacent design space in cortical-inspired computation. SC is built from biologically inspired “cells” arranged in regions and uses binary stimuli, synapses that store an address and permanence, dendrites with overlap thresholds, neuron-level activation and prediction thresholds, inhibition via a global or local k-winner scheme, and boosting for under-utilized neurons (Giorgio, 2017). Learning is Hebbian-style: for each active neuron, synaptic permanence is incremented toward co-active inputs, decremented away from missing inputs, and synapses with zero permanence are reassigned to randomly chosen active stimuli not already used by that neuron.

Its processing cycle is organized as online encode, learn, predict, and decode steps. Sequential and contextual patterns are handled by feeding back neuron activations as a second stimuli vector, allowing a neuron’s second dendrite to watch which neurons fired at the previous time step. In the Ball Demo, the first stimulus is a $512 \times 27$5 pixel occupancy map, the first forest uses 50 synapses per dendrite to learn spatial snapshots, and a second forest with 1-synapse dendrites learns transitions; after training on bouncing trajectories, the model can forecast 20 time steps ahead by looping Predict and Decode.

Implementation details further distinguish SC from the SimCortex systems above. The reference implementation is in C++ with OpenCL 1.2 and runs on Windows and Linux across CPU and GPU hardware. The demo architecture uses 1.5 million neurons, 3 million dendrites, 75 million synapses in one forest, and 1.5 million synapses in a second forest. On an NVIDIA GTX 1070, mean performance over 100 000 time steps is 6.72 ms/frame for Encode only, 7.44 ms/frame for Encode + Learn, and 21.76 ms/frame for Encode + Learn + 20×(Predict+Decode); the reported throughput is approximately 10 billion synapses per second, with the “move synapses” portion of Learn identified as the current bottleneck.

Taken together, these systems indicate that cortex-inspired research is being operationalized in at least three different ways: as distributed event-driven neural simulation, as structurally abstracted neuromorphic hardware, and as topology-constrained geometric reconstruction. A common misconception is that SimCortex refers to a single software package or a single algorithmic lineage. The literature summarized here does not support that view. Instead, the term designates distinct systems whose shared reference to cortex is architectural or anatomical rather than genealogical.