NeuroSim: CIM Benchmarking and Simulation

• NeuroSim is a simulation and benchmarking framework for compute-in-memory accelerators that integrates neural-network execution, device non-idealities, and chip-level hardware metrics.
• It employs a two-part system with a PyTorch behavioral simulator and a C++ hardware analyzer to automatically map networks to hardware and evaluate performance.
• The framework supports mode-specific functions such as on-chip training and non-ideality injection, optimizing energy, latency, area, and throughput in modern AI accelerators.

NeuroSim, and the closely related spellings Neurosim and NeuroSIM, denotes several distinct research systems. In recent arXiv literature, the most extensively specified usage is an open-source benchmarking framework for compute-in-memory (CIM) accelerators, especially analog compute-in-memory (ACIM) systems, where it bridges neural-network execution, device- and circuit-level non-idealities, and chip-level power, performance, and area estimation (Read et al., 5 May 2025). In parallel, the name also appears in neuromorphic robotics as a real-time sensor-and-dynamics simulator for event-based perception (Das et al., 16 Feb 2026), and in neuro-symbolic vision-language work as a weakly supervised image-manipulation system called NeuroSIM (Singh et al., 2023). The dominant technical lineage, however, is the CIM benchmarker built around NeuroSim and DNN+NeuroSim (Peng et al., 2020).

1. NeuroSim as a compute-in-memory benchmarking framework

NeuroSim is designed to evaluate CIM accelerators across multiple abstraction layers at once: neural-network behavior, memory-device and circuit non-idealities, and hardware implementation metrics such as area, latency, energy, throughput, and efficiency (Read et al., 5 May 2025). In its recent form, NeuroSim V1.5 is described as a two-part system consisting of a behavioral simulator in PyTorch and a hardware analyzer in C++, with support for linear, convolutional, recurrent, and transformer models, TensorRT post-training quantization, flexible noise injection, expanded device support including non-volatile capacitive memories, and runtime improvements of up to 6.5x relative to V1.4 (Read et al., 5 May 2025).

The earlier DNN+NeuroSim V2.0 line established the end-to-end pattern that remains characteristic of the framework: a Python wrapper interfaces PyTorch training or inference with the NeuroSim hardware core, performs automatic algorithm-to-hardware mapping, collects traces of activations and weights, and reports both accuracy and chip-level metrics (Peng et al., 2020). V2.0 emphasized on-chip training, adding explicit models of update nonlinearity, asymmetry, device-to-device variation, and cycle-to-cycle variation, together with peripheral support for error computation and weight-gradient computation (Peng et al., 2020).

A defining feature of the NeuroSim family is that it does not treat accuracy and hardware cost as separable. Instead, it is built to answer whether a given device, array organization, peripheral design, and quantization scheme can sustain acceptable network behavior while also meeting system-level efficiency targets (Read et al., 5 May 2025).

2. Architectural hierarchy and computational workflow

The framework models CIM hardware hierarchically from device/transistor/cell to sub-array, processing element or tile, interconnect, and chip, with automatic mapping of network layers onto arrays and floorplanning at the architecture level (Zhou et al., 2 Jan 2025). For current-domain arrays, the analog multiply-accumulate operation is represented as

$I_{BL_i} = \sum_j G_{ij} V_j,$

where $G_{ij}$ is the stored conductance and $V_j$ is the input voltage; for charge-domain arrays the corresponding abstraction is

$Q_{BL_i} = \sum_j C_{ij} V_j,$

where $C_{ij}$ is the programmable capacitance (Read et al., 5 May 2025).

The V1.5 software flow is explicitly staged: quantization, unfolding of mapped layers, array mapping, analytical analog MAC computation, non-ideality injection, shift-and-add according to bit significance, accumulation and concatenation across hierarchy, folding back to tensor form, and dequantization (Read et al., 5 May 2025). This organization allows the same run to produce model-level accuracy and trace-driven hardware estimates. In device expert mode, weights are mapped to conductance or capacitance states and non-idealities are applied at the memory-state level; in circuit expert mode, ideal partial sums are computed first and then perturbed using pre-characterized statistical output distributions stored in output_noise.csv (Read et al., 5 May 2025).

Representative hardware studies show how this workflow is used in practice. In TReCiM, NeuroSim is not used as a single-array calculator but as an end-to-end benchmarking engine: SPICE and device simulation first derive the behavior of a temperature-resilient subthreshold FeFET CiM primitive; the extracted electrical and circuit parameters are then embedded into NeuroSim; the simulator’s hierarchy of subarrays, ADCs, tiles or PEs, interconnect, and chip organization is finally used to obtain inference accuracy, energy, area, throughput, and TOPS/W for VGG-8 on CIFAR-10 (Zhou et al., 2 Jan 2025). The same paper describes the modeled cell as a multibit, temperature-resilient, subthreshold FeFET CiM array built from a 2FeFET-1T cell and benchmarked at system level after calibration with SPICE-derived parameters (Zhou et al., 2 Jan 2025).

3. Modeling device and circuit non-idealities

A central reason NeuroSim is used in CIM research is its treatment of non-ideal behavior. In V1.5, device expert mode supports device-to-device variation, stuck-at-faults, and temporal drift. Device variation is represented state-wise as

$G = N(G_{mean_i}, \sigma_i),$

and temporal drift is modeled as

$G(t) = G_0 (t/t_0)^v.$

In circuit expert mode, users can instead inject SPICE- or silicon-derived MAC-output statistics, which lets complete array-plus-peripheral behavior be folded into fast behavioral simulation (Read et al., 5 May 2025).

For on-chip training, DNN+NeuroSim V2.0 introduces explicit analog update models. The conductance trajectories for potentiation and depression are given as

$G_{LTP} = B (1 - e^{-P/A}) + G_{min},$

$G_{LTD} =- B (1 -e^{(P-Pmax)/A} ) + G_{max},$

with

$B = \frac{G_{max} - G_{min}}{1 - e^{-Pmax/A}},$

where $G_{ij}$0 is the number of update pulses and $G_{ij}$1 controls nonlinearity (Peng et al., 2020). The same framework benchmarks the impact of nonlinearity, asymmetry, device-to-device variation, and cycle-to-cycle variation during training, and concludes that the preferred device specifications for analog on-chip training are cycle-to-cycle variation < 1%, on-state resistance $G_{ij}$2, write pulse width < 1 $G_{ij}$3, and nonlinearity below $G_{ij}$4 (Peng et al., 2020).

A separate training-oriented study using DNN+NeuroSim to compare Backpropagation and Direct Feedback Alignment on CIM hardware reinforces the same cross-layer point. In that work, ADC precision, subarray size, quantization, and update variability are analyzed together with training behavior; 1-bit ADC causes training to stop, 2-bit ADC does not exceed the random-guessing threshold in the reported DFA setting, and cycle-to-cycle variation is markedly more harmful than static device-to-device variability (Wolters et al., 2022). The same study reports that about 95% of training energy is attributed to off-chip buffer accesses and about 91% of latency to buffering intermediate results, illustrating that NeuroSim frequently exposes system bottlenecks outside the memory array itself (Wolters et al., 2022).

4. Extensions, derivatives, and representative deployments

A substantial ecosystem now sits around NeuroSim rather than inside it. MICSim is presented as a modular refactor and extension of NeuroSim that preserves silicon-validated hardware models from DNN+NeuroSim v1.3 and the hierarchical subarray → PE → tile organization, while restructuring the simulator in a Python-centered, object-oriented form with native support for PyTorch, HuggingFace Transformers, CNNs, and Transformers (Wang et al., 2024). MICSim also adds a statistic-based average mode that achieves 9x–32x runtime speedup relative to NeuroSim while showing less than 10% difference in energy efficiency and minimal throughput impact on the reported CNN benchmarks (Wang et al., 2024).

Several hardware papers use NeuroSim as the system-level back end for concrete accelerator studies. DetectX evaluates an adversarial-input detector built around the sum of column currents in a NeuroSim-like analog crossbar architecture, integrates a custom 32 nm CMOS detector with the NeuroSim-modeled crossbar pipeline, and reports 10x–25x more energy efficient detection than prior neural detector baselines together with ROC-AUC > 0.95 for many strong attacks (Moitra et al., 2021). XploreNAS uses NeuroSim not in the architecture-search loop itself but as the post-search hardware evaluation backend, reporting that searched subnets can achieve about 1.5–1.6x lower EDAP than a ResNet-18 baseline on non-ideal ReRAM crossbars (Bhattacharjee et al., 2023). A study of ImageNet-scale binary neural networks on NVM crossbars uses NeuroSim to show that 8-bit ADC resolution with 4-bit first-layer input precision is a near-optimal deployment point, and that ADC area, buffer latency, and interconnect dynamic energy dominate different hardware metrics (Huang et al., 2023).

NeuroSim is also increasingly used as one layer in heterogeneous validation stacks rather than as a standalone oracle. In the 2026 study of nonvolatile charge-domain attention with HZO ferroelectric capacitors, NeuroSim is used specifically for ADC + peripheral energy inside a broader methodology that also employs ngspice, CrossSim, and FiPy (Abouagour, 27 May 2026). That paper states that the four tools are cross-checking implementations of the same analytic model, and reports 19.22 fJ/MAC for the V-DAC FCDC tile and 0.78 fJ/MAC for the PWM variant, with the caveat that cross-tool agreement is a consistency check rather than physical validation (Abouagour, 27 May 2026).

5. Automation, optimization, and the widening NeuroSim ecosystem

The growth of NeuroSim’s parameter space has led to automation layers. ChatNeuroSim is an LLM-agent framework built explicitly on top of NeuroSim V1.5 for automated CIM deployment and optimization (Lee et al., 4 Mar 2026). It introduces a Task Parsing Agent, Parameter Parsing Agent, and Parameter Adjustment Agent, together with schemas for simulator and optimizer parameters, script generation, and optimization algorithms including SA, GA, and TPE (Lee et al., 4 Mar 2026). In a 40-query request benchmark, the framework reports 100% correct runnable-script generation with GPT-5.1, and for Swin Transformer Tiny under 22 nm it reports pruning-based optimization that reduces average runtime to 0.42x–0.79x of the no-pruning baseline, depending on the target metric (Lee et al., 4 Mar 2026).

The following systems illustrate how the name has broadened across adjacent literatures:

System	Domain	Distinguishing feature
NeuroSim (Read et al., 5 May 2025)	CIM benchmarking	TensorRT PTQ, device/circuit non-idealities, PPA
MICSim (Wang et al., 2024)	NeuroSim-derived CIM simulation	Modular Python refactor; CNNs and Transformers
ChatNeuroSim (Lee et al., 4 Mar 2026)	NeuroSim automation	LLM-agent parsing, execution, and DSE pruning
Neurosim (Das et al., 16 Feb 2026)	Neuromorphic robotics	Real-time multimodal sensor and multirotor simulation
NeuroSIM (Singh et al., 2023)	Neuro-symbolic vision-language	Multi-hop image manipulation from language

This expansion has made the name semantically broad. In the CIM literature, “NeuroSim” refers to a hardware-software co-design framework; in robotics, “Neurosim” denotes a real-time simulator for event cameras and agile vehicles; in vision-language research, “NeuroSIM” denotes a weakly supervised neuro-symbolic manipulator (Das et al., 16 Feb 2026).

6. Other meanings of “Neurosim” and the broader neuro-simulation context

Outside CIM, the title “Neurosim: A Fast Simulator for Neuromorphic Robot Perception” designates a markedly different system: a real-time, high-performance library for simulating dynamic vision sensors, RGB cameras, depth sensors, inertial sensors, and multi-rotor vehicle dynamics, integrated with a ZeroMQ-based communication layer called Cortex (Das et al., 16 Feb 2026). That system reports frame rates of about 2700 FPS on an NVIDIA RTX 4090 GPU, event-simulation rates of >31 kHz for VGA and >23 kHz for HD, and end-to-end closed-loop controller latency below 0.7 ms even at 5 kHz control rate (Das et al., 16 Feb 2026). The same paper frames Neurosim as a streaming-first platform for online training and closed-loop testing rather than a dataset generator (Das et al., 16 Feb 2026).

In neuro-symbolic multimodal AI, the abstract of “Image Manipulation via Multi-Hop Instructions” introduces NeuroSIM as an extension of Neuro Symbolic Concept Learning (NSCL) for image manipulation from natural-language instructions. It is described as weakly supervised, capable of complex multi-hop reasoning over multi-object scenes, and driven by a symbolic program in a domain-specific language of object attributes and manipulation operations (Singh et al., 2023).

Separate neighboring abbreviations are sometimes confused with NeuroSim but denote different constructs. NSIM, the Neurogram Similarity Index Measure, is an objective metric for comparing auditory-nerve neurograms in simulated hearing loss and cochlear neural degeneration (Cheema et al., 15 Jun 2025). SIM, in the fMRI literature, is a surface-based multimodal decoding framework that aligns cortical activity, video, and audio embeddings for inter-subject movie decoding (Dahan et al., 27 Jan 2025). More broadly, the neuroscience-simulation literature argues for families of simulators spanning multicompartment models, point-neuron networks, and population models, with multimodal prediction of spikes, electric, magnetic, and optical signals (Einevoll et al., 2019). Platforms such as Digital Twin Brain extend that ambition to whole-brain spiking simulation with 86 billion neurons and 47.8 trillion synapses, personalized using sMRI, DTI, and PET (Lu et al., 2023).

Taken together, these usages show that “NeuroSim” is not a single universally fixed referent. In current technical practice, it most often denotes a CIM accelerator benchmarker, but it also names systems for neuromorphic robot perception and neuro-symbolic reasoning, and it sits within a wider research tradition that uses simulation to connect neural computation, hardware realization, and biological or embodied data (Read et al., 5 May 2025).