Reconfigurable Lookup Architecture

• Reconfigurable lookup architecture is a design family where lookup state is stored in tunable tables with configurable placement, addressing, and update mechanisms.
• In FPGA systems, distributed local configuration reduces routing congestion and enhances operating frequency compared to global register maps.
• Across domains like machine learning, photonics, and quantum computing, leveraging precomputed lookup tables yields improvements in area efficiency, speed, and energy consumption.

A reconfigurable lookup architecture is an organization in which functionality is determined by stored tables or configuration bits, while the storage, addressing, and update mechanisms for those tables remain architecturally tunable. In FPGA literature, the term denotes not only the LUT primitive itself but also the way configuration state is physically placed and distributed so that modules locally “look up” their operating mode, an approach made explicit by distributed settings-register architectures that replace a monolithic global register bank with bus-programmed local memories (Beasley, 2020). In the broader literature, the same architectural idea appears in technology mapping for $K$-LUT fabrics, LUT-based machine-learning accelerators, photonic ROM engines, quantum lookup oracles, packet-lookup pipelines, and processor-integrated reconfigurable instruction fabrics (Yu, 15 Jul 2025).

1. Conceptual scope

At the primitive level, a LUT is a small reconfigurable memory implementing a Boolean function of bounded fan-in. In FPGA technology mapping, LUT mapping is “the process of translating a given Boolean network into a network composed of $k$-input LUTs ($k$-LUTs), where $k$ is the maximum number of inputs each LUT can handle,” and a $K$-LUT is modeled as a memory storing $2^K$ output bits for a function $f:\{0,1\}^K \to \{0,1\}$ (Yu, 15 Jul 2025). A reconfigurable lookup architecture extends that primitive notion to the architectural level: it specifies where lookup state resides, how it is addressed, how it is updated, and how it is embedded into a larger datapath or control network (Beasley, 2020).

Domain	Lookup object	Reconfigurable locus
FPGA control	Local settings registers	Common bus, local memory maps, Ready handshake (Beasley, 2020)
Logic synthesis	$K$-LUT network	Cut selection and cell subset in mapping flow (Yu, 15 Jul 2025)
ML accelerators	LUT cores, LUT trees, per-edge activations	$\mu, L, K$, bit-widths, tile shape, learned mappings (Geens et al., 28 Apr 2026)
Photonic and quantum systems	Banked optical ROM, oracle LUT	Function-select paths, bank enables, $\lambda,\gamma$ parameters (Singh et al., 5 May 2026)

This breadth matters because it separates the lookup abstraction from any single implementation substrate. In one line of work, lookup state is a distributed register bank controlling FPGA modules; in another, it is a precomputed tensor of ternary partial sums; in another, it is a banked optical ROM encoded in microring resonators; and in another, it is a parameterized quantum oracle implementing $k$0 (Beasley, 2020, Geens et al., 28 Apr 2026, Singh et al., 5 May 2026, Zhu et al., 2024).

2. Distributed local configuration in FPGA fabrics

The clearest FPGA-specific formulation appears in the distributed memory, local configuration architecture of (Beasley, 2020). The baseline “global” design uses a single central settings register block populated by a host controller; modules consume configuration words through wide multi-bit buses, often with added output register stages, CDC synchronization chains, and destination registers. The alternative architecture removes the central register map and replaces it with a common configuration bus, a decode module, and multiple slave modules, each with its own local configuration register set, a uniform bus interface carrying addressing, data, write strobe, and a Ready handshake, and logic controlled by those local registers (Beasley, 2020).

The architectural significance of this substitution is primarily physical. Under a global map, configuration bits fan out from a single location, producing high-fan-out nets, routing congestion, and timing pressure; under the distributed design, configuration is delivered as transactions on a relatively narrow shared bus, while local control signals remain short because the registers that drive them sit near the functional logic. The same organization is explicitly designed to work in multiple clock domains and in dynamic partial reconfiguration, because writes occur only when a module indicates a safe state and a new partial module need only expose the same configuration interface to the shared bus (Beasley, 2020).

The measured implementation results on an Intel Cyclone V (5CSXFC6D6F31C8) in Quartus Prime 19.1 are correspondingly concrete. For 226 target registers per slave, a distributed implementation used $k$1 ALMs, $k$2 registers, and $k$3 ALUTs, versus $k$4 ALMs, $k$5 registers, and $k$6 ALUTs for the compared global design with maximum routing-register stages; the distributed design is therefore about 25% of the ALMs and about 20% of the registers of that global alternative (Beasley, 2020). Maximum operating frequency is reported as about $k$7 for the distributed memory architecture and just under $k$8 for the global memory architecture with routing registers (Beasley, 2020).

The same paper also makes clear that the configuration memories in those experiments are implemented as distributed registers in ALMs rather than block RAMs. This matters because the architecture is not merely a logical register map split across modules; it is a deliberate physical localization of lookup state, intended to reduce long routes, CDC scaffolding, and the replication cost associated with global settings networks (Beasley, 2020).

3. Lookup-centric compute architectures for machine learning

In machine-learning accelerators, reconfigurable lookup architecture usually means that arithmetic is replaced, partially or wholly, by precomputed table access, and that the key structural parameters of those tables are exposed as design variables. For ternary LLM inference, one such architecture groups $k$9 activations, precomputes all required ternary partial sums during a LUT Build Phase, and then replaces multiplication by indexed lookup, optional sign inversion, and accumulation during a Fetch & Accumulate Phase. The architecture is explicitly parameterized by four design parameters—$k$0, $k$1, $k$2, and activation data type—and a hardware generator spans that full space; the same study reports that the optimal architecture is fundamentally governed by the activation data type, that maximizing core size consistently improves area density, that optimized designs achieve a 2.2x area reduction compared to multiplier-based baselines, and that correcting suboptimal parameters yields up to a 1.2x area improvement (Geens et al., 28 Apr 2026).

A second line of work uses lookup tables to realize learned nonlinearities or larger neural primitives directly on FPGA. An FPGA-based design for learned activation functions in Kolmogorov-Arnold Networks discretizes each learned activation $k$3 into a lookup table, couples that with fine-grained quantization, and regenerates the FPGA bitstream for new activation sets; evaluations report superior computational speed and over $k$4 times higher energy efficiency compared to edge CPUs and GPUs while maintaining matching accuracy and minimal footprint overhead (Yin et al., 23 Aug 2025). NeuraLUT-Assemble realizes dense sub-neural networks as Boolean lookup tables and then assembles them into configurable LUT trees, combining mixed-precision techniques, learned mappings, and skip-connections across entire LUT structures; it reports up to $k$5 reduction in area-delay product compared to the state of the art at the time of publication (Andronic et al., 1 Apr 2025). PolyLUT-Add addresses wide-input neurons by decomposing them into $k$6 smaller PolyLUT sub-neurons plus an adder layer, reporting a LUT reduction of $k$7 with a $k$8 decrease in latency for similar accuracy (Lou et al., 2024).

A third line focuses on scalable mapping of quantized networks into LUT fabrics rather than on individual nonlinearities. TLMAC compiles quantized neural networks so that groups of fixed weights are encoded into lookup-based processing elements, with clustering and route reduction used to increase reuse and reduce congestion; the framework reports that its efficient logic mapping and reuse enable entire ImageNet-scale quantised models with full-precision accuracy to be implemented using lookup-based computing on one commercially available FPGA (Gerlinghoff et al., 2024). Vec-LUT, by contrast, reconfigures the lookup access pattern for parallel ultra-low-bit LLM inference on CPUs: instead of scalar $k$9 lookups per token, it constructs a unified lookup table across parallel tokens and performs a single $k$0 vector lookup per index, together with a vector LUT-centric tensor layout and cache-aware streamed lookup, yielding up to $k$1 speedup on five edge devices across three LLMs (Li et al., 6 Dec 2025).

Taken together, these designs establish that “reconfigurable” in lookup-centric ML hardware can refer to compile-time parameters such as group size and tile shape, per-edge quantization and LUT contents, learned connectivity and tree topology, or the memory layout and granularity of lookup itself (Geens et al., 28 Apr 2026, Yin et al., 23 Aug 2025, Andronic et al., 1 Apr 2025, Lou et al., 2024, Gerlinghoff et al., 2024, Li et al., 6 Dec 2025).

4. Technology mapping and the effective LUT fabric

Reconfigurable lookup architecture is not determined solely by physical tables; it is also shaped by the mapping flow that decides how Boolean logic is presented to those tables. In FPGA CAD, the Boolean network is modeled as a DAG, cuts are enumerated at each node, and a $k$2-feasible cut with $k$3 corresponds to a potential LUT implementing the logic from leaves to root. FuseMap exploits this by interleaving ASIC standard-cell mapping and LUT mapping, using reinforcement learning to choose a subset of standard cells before applying if -K 6 and mfs2, with reward functions based on LUT count, depth, or area-delay product (Yu, 15 Jul 2025).

The reported results show that this pre-LUT restructuring materially changes the effective architecture of the same physical 6-LUT fabric. Across 24 ASAP7 designs, FuseMap reduces LUT count in 20 designs, with average LUT reduction of about 9%; average delay improvement is about 3%; average ADP improvement is about 9%; and over 161 designs from ISCAS89, EPFL, and VTR, the reported average ADP improvement remains about 9% (Yu, 15 Jul 2025). The architectural implication is that LUT efficiency is jointly determined by table resources and by the decomposition presented to the mapper, not by LUT size alone.

This complicates a common simplification that equates a lookup architecture with the bare presence of configurable LUT cells. The same 6-LUT fabric can behave differently, in area and depth, when the pre-mapping logical primitive set is altered. A plausible implication is that future lookup architectures may increasingly be co-designed with mapping flows, rather than treated as a fixed substrate onto which logic is merely projected (Yu, 15 Jul 2025).

5. Photonic and quantum variants

The same architectural vocabulary appears in non-electronic settings. OptiLookUp is a reconfigurable photonic ROM architecture using integrated microring resonators on the GlobalFoundries 45SPCLO silicon photonics platform. The memory array is organized as four banks, each a $k$4 MRR sub-array; two MSBs select one of the four banks; each bank has four word lines; and outputs can be read either as digital optical bits or as a weighted analog photocurrent through MMI combiners and a photodiode. Reconfigurability is achieved with transistor-based optical selectors that enable banks or bias individual rings without physical light rerouting. The reported simulations show reliable operation at data rates up to $k$5, about $k$6 settling latency, and $k$7, and the same ROM can implement sigmoid, tanh, ReLU, and exponential mappings (Singh et al., 5 May 2026).

In quantum computing, the lookup primitive becomes an oracle. A unified architecture for a quantum lookup table implements

$k$8

and is parameterized by $k$9 and $K$0, which control the tradeoff among qubit count, non-Clifford gates, depth, and infidelity under local 2D connectivity. The framework recovers QROM-like and bucket-brigade-like regimes as parameter choices and also identifies a regime with simultaneous sublinear scaling, namely $K$1, $K$2, and infidelity $K$3 for constant word size (Zhu et al., 2024).

These examples show that the defining features of a reconfigurable lookup architecture are substrate-independent: banked organization, explicit selectors or decoders, tunable placement of lookup state, and formal tradeoffs between storage, latency, and the cost of accessing or rewriting that state (Singh et al., 5 May 2026, Zhu et al., 2024).

6. Packet lookup, pipeline fabrics, and reconfigurable instructions

Lookup architecture also appears in packet-processing and processor microarchitecture. In SDN flow lookup, the Range-based Ternary Search Tree organizes each node as a 3-node with two ordered data fields and three children corresponding to ranges; a parallel multi-pipeline FPGA implementation maps the tree into pipeline stages, uses pointer elimination through arithmetic address generation, and supports modification, deletion, and insertion through write bubbles and valid bits. On a state-of-the-art FPGA, the reported design achieves 670 Million Packets Per Second for a 1 K 15-tuple flow-table and a memory efficiency of 1 byte of memory for each byte of flow (Hatamia et al., 2018).

A closely related but more general pipeline view appears in bidirectional SRAM pipelining for trie and decision-tree traversal. There, search trees are partitioned into subtrees that may be mapped in forward or reverse direction onto a dual-port linear pipeline, with a bidirectional fine-grained mapping algorithm and inversion factor used to balance memory across stages. The reported architecture can store a full backbone routing table with 154419 entries using 2MB of memory and sustain 1.87 billion packets per second, corresponding to 0.6 Tbps for minimum-size packets, and up to 2.4 Tbps with caching (Jiang et al., 2011).

Modern network processors motivate a different formulation, the CRAM lens, which models lookup as a DAG of TCAM and SRAM steps and uses that model to design scalable IPv4 and IPv6 schemes. Under this framework, RESAIL scales to 2.25 million IPv4 prefixes on Tofino-2 while a pure TCAM approach supports only 250k prefixes, and BSIC scales to 390k IPv6 prefixes on Tofino-2, supporting 3.2 times as many prefixes as a pure TCAM implementation; MashUp provides a hybrid TCAM/SRAM trie formulation with configurable strides and node types (Chang et al., 4 Mar 2025).

At the processor level, LUTstructions embed a small LUT-based virtual FPGA into a softcore and let bitstreams implementing custom instructions load from main memory through a dedicated bitstream cache. The design is tailored to low-latency custom instructions and wide reconfiguration, achieves up to 38.4 GB/s effective reconfiguration throughput, reports no notable operating frequency overhead, and demonstrates microbenchmark speedups of 2.55x for popcount, 13.4x for a bitwise permutation plus XOR, and 2.86x even under an always-miss alternating-bitstream pattern (Papaphilippou, 24 Feb 2026).

7. Recurring trade-offs and interpretive themes

Across these literatures, several recurrent trade-offs define the field. First, centralization competes with locality. In FPGA configuration networks, a global settings map simplifies logical organization but creates large fan-out nets and routing-register overhead, whereas distributed local memories reduce routing complexity and improve $K$4 (Beasley, 2020). Second, table width competes with hierarchy. In ternary accelerators and LUT-based neural inference, increasing $K$5 or fan-in improves reuse or expressivity but grows LUT depth, MUX size, and build cost, motivating tree decomposition, additive decomposition, or hybrid bit-serial formulations (Geens et al., 28 Apr 2026, Andronic et al., 1 Apr 2025, Lou et al., 2024, Gerlinghoff et al., 2024).

Third, lookup throughput competes with memory behavior. Vec-LUT identifies that scalar LUT inference underutilizes memory bandwidth in multi-token settings and addresses that by changing the lookup unit from scalar to vector and by reconfiguring tensor layout and cache behavior (Li et al., 6 Dec 2025). Fourth, compactness competes with dynamic flexibility. Quantum lookup tables expose this explicitly through $K$6 and $K$7, which trade qubits, $K$8-count, and error; CRAM-guided packet lookup makes the analogous trade among TCAM, SRAM, and stage depth; and FPGA-based learned-activation engines obtain high efficiency but rely on deployment-time regeneration of LUT contents and bitstreams rather than runtime structural adaptation (Zhu et al., 2024, Chang et al., 4 Mar 2025, Yin et al., 23 Aug 2025).

This suggests that “reconfigurable lookup architecture” is best understood not as a single canonical structure but as a design family. What unifies that family is the treatment of precomputed or programmable lookup state as a first-class architectural resource, together with explicit mechanisms for placing, selecting, updating, and composing that state under constraints imposed by routing, memory hierarchy, timing closure, power, or error models (Beasley, 2020, Geens et al., 28 Apr 2026, Yu, 15 Jul 2025, Singh et al., 5 May 2026, Zhu et al., 2024).