Quality Indicator Circuits for Noisy Quantum Hardware
- Quality Indicator Circuits (QICs) are specialized probe circuits with a known ideal outcome, designed to diagnose layout noise on NISQ devices.
- They retain the original circuit’s 2-qubit interaction structure in a shallower form to enable rapid, hardware-specific noise evaluation.
- QICs offer significant experimental savings, reducing hardware run overhead by up to 79.7% compared to conventional methods.
Quality Indicator Circuits (QICs) are small, structure-preserving probe circuits for real-time assessment of layout quality on noisy quantum hardware. In the formulation proposed for near-term devices, a QIC is any circuit whose ideal noise-free outcome is known a priori or can be easily computed; it is designed to retain the basic structure of the user’s circuit, usually in shallower form, and is executed on candidate physical layouts so that deviation from the ideal outcome serves as a direct indicator of layout-dependent noise (Srivastava et al., 23 Sep 2025). Within this literature, QICs address a specific NISQ problem: the output quality of a mapped circuit depends not only on the abstract algorithm but also on which physical qubits and couplings are used, because noise is both non-uniform and dynamic (Srivastava et al., 23 Sep 2025).
1. Layout selection as the motivating problem
The QIC framework is motivated by the observation that two layouts can be functionally equivalent and still produce materially different results on hardware. The cited study illustrates this with a 6-qubit QAOA instance in which two isomorphic layouts with identical gate structure and SWAP count yield expectation values of about $0.481$ and $0.383$, while the ideal value is $0.522$; a violin plot over 104 isomorphic layouts shows a wide spread in quality (Srivastava et al., 23 Sep 2025). This directly challenges the common reduction of layout selection to SWAP minimization alone.
The same work positions QICs against two existing approaches. Mapomatic is lightweight because it uses backend calibration data and requires no extra hardware runs, but it depends on noise estimates that can become stale, with calibration updates only every 3–24 hours. JIT transpilation addresses staleness by performing hardware-side characterization, but it profiles the whole device rather than only the region relevant to the user circuit; the paper cites about 132 circuit executions for a 27-qubit IBM device and roughly 4 minutes of hardware time on a 127-qubit device (Srivastava et al., 23 Sep 2025). QICs are introduced as an intermediate strategy: real-time like JIT, but targeted like calibration-based selection.
2. Definition and circuit construction
A QIC is defined as any circuit whose ideal noise-free outcome is known a priori or can be easily computed. In the construction proposed for layout selection, the QIC is designed to satisfy three properties: it retains the basic 2-qubit interaction structure of the user’s circuit, it has a known ideal output, and it is usually shallower than the original circuit (Srivastava et al., 23 Sep 2025).
The construction proceeds by placing a layer of Hadamard gates on all qubits, then a network of CNOTs derived from the user circuit’s 2-qubit gate pattern, followed by another layer of Hadamards on all qubits. The algorithm scans the user circuit, counts the 2-qubit gates between qubit pairs, and then creates a simplified CNOT network with the same interaction template; the paper states that the construction uses a minimal repetition rule based on the least frequent pair count (Srivastava et al., 23 Sep 2025).
For this specific construction, the ideal output is always
The reason given is structural: the first Hadamards prepare a uniform superposition, a network of CNOTs preserves that uniform superposition, and the final Hadamards map it back to the all-zero state (Srivastava et al., 23 Sep 2025). The QIC therefore does not attempt to compute the user algorithm’s answer. Its purpose is diagnostic: it acts as a compact structural probe for the noise sensitivity of candidate layouts.
3. Scoring and interpretation
Because the ideal output is known, layout scoring is immediate. If a QIC is executed for shots and the ideal outcome appears times, the score is
Higher score means a better layout (Srivastava et al., 23 Sep 2025). The same paper also notes that observables can be used instead of raw bitstring probability. For an -qubit path-structured circuit, the score used throughout the study is
This makes QIC scoring compatible with workloads whose natural outputs are expectation values rather than single bitstrings (Srivastava et al., 23 Sep 2025).
The validity claim for QICs is empirical rather than axiomatic. On fake backends, layouts that score better under QIC tend to yield original-circuit expectation values closer to the ideal value. The method is described as especially relevant for structured circuits such as QAOA, VQE, Hamiltonian simulation, and some QML circuits, where the same interaction pattern repeats over layers; the QIC remains compact because it preserves the entangling structure without inheriting full algorithmic depth (Srivastava et al., 23 Sep 2025). The paper further reports that QIC remains a reliable ranking signal even as circuit depth increases.
4. Selection procedures: per-layout, Union QIC, and Overlap QIC
The basic procedure is straightforward: generate one QIC for each isomorphic layout, execute each QIC on hardware, and choose the layout with the best QIC score. This yields current, layout-specific information, but hardware cost can still be substantial when many isomorphic layouts exist (Srivastava et al., 23 Sep 2025).
To reduce that cost, the paper introduces Union QIC. If two layouts share no physical qubits, they can be combined into one larger probe circuit, and the result for each original QIC can be recovered by marginalizing over the other qubits. The paper formulates the problem of partitioning layouts into the minimum number of disjoint sets as NP-hard and therefore uses a greedy heuristic: process layouts in random order, place each layout into the first set it is disjoint from, and otherwise create a new set (Srivastava et al., 23 Sep 2025). The benefit is fewer hardware runs; the limitation is that savings diminish when disjoint layouts become rare.
The second refinement is Overlap QIC with a distortion threshold. Instead of requiring zero overlap, this method allows overlapping layouts provided that the resulting union does not distort the original per-layout structure too much. Distortion is defined as the change in the number of 2-qubit gates associated with a physical qubit in the union QIC compared to the individual QIC, and a threshold determines admissibility (Srivastava et al., 23 Sep 2025). The paper states that, for each qubit pair in the union, the number of CNOTs is set to the ceiling of the average number across participating layouts. This creates a controlled trade-off: more aggressive packing reduces executions, but excessive overlap risks weakening the correspondence between the union probe and the original layouts.
5. Reported performance and hardware overhead
The reported reductions in circuit-execution overhead are central to the QIC proposal. For QAOA circuits on a 27-qubit backend, JIT requires 132 executions, whereas the reported counts for the three QIC variants are as follows (Srivastava et al., 23 Sep 2025):
| Method | Reported executions |
|---|---|
| JIT | $0.383$0 |
| Basic QIC | $0.383$1 |
| Union QIC | $0.383$2 |
| Overlap QIC, threshold $0.383$3 | $0.383$4 |
These examples correspond to 6, 10, 14, 18, and 20 qubits. The headline result is that Overlap QIC reduces hardware overhead by 79.7% on average compared with JIT (Srivastava et al., 23 Sep 2025).
The same paper also reports a direct comparison with Mapomatic on a 127-qubit ibm_sherbrooke device. For a 6-qubit $0.383$5 QAOA circuit, QIC executed 4 union QICs in about 12 seconds for 28 isomorphic layouts and selected a layout that produced a better expectation value than the layout selected by Mapomatic; the experiment was run about 47 minutes after calibration, so the calibration data had become stale (Srivastava et al., 23 Sep 2025). The advantage decreases as circuit size grows, and the authors attribute that reduction to noisier raw results and to the shrinking number of available isomorphic layouts. The framework is therefore lightweight, but not cost-free, and its gains are structure- and regime-dependent.
6. Relation to broader quality-aware quantum-circuit methods
A related line of work concerns hardware-aware training of parameterized quantum circuits, even when the term “QIC” is not used explicitly. One such study models device quality through $0.383$6 relaxation time, $0.383$7 dephasing time, single-qubit gate error, multi-qubit gate error, and readout/output fidelity, and it argues that temporal variation in these metrics causes circuits trained under one noise profile to become stale over time (Alam et al., 2019). Its proposed classical training approach simulates the target hardware with measured qubit quality metrics, averages those metrics over 43 days after outlier removal by the interquartile range rule, and reports that fidelity on IBMQX4 can improve by as much as 42.5% for iris classifiers relative to ideal simulation-based training (Alam et al., 2019).
This suggests a broader methodological family in which quantum-circuit design, training, and mapping are conditioned on device-specific quality indicators rather than on static abstractions. Within that broader family, QICs specialize in targeted, real-time layout-noise estimation rather than parameter optimization. Their defining distinction is that they use small probe circuits with known ideal outcomes to rank layouts directly on hardware, rather than constructing a full noise model and retraining parameters (Srivastava et al., 23 Sep 2025).
7. Terminological breadth and unrelated uses of “QIC”
The expression “Quality Indicator Circuits” is not uniform across the literature. In RF and microwave analysis, one paper uses “quality indicator circuits” to describe constant quality factor contours on 2D and 3D Smith charts: for passive circuits with positive resistance, constant-$0.383$8 contours are circle arcs inside the 2D Smith chart and semi-circles in the north hemisphere of the 3D Smith chart; for active circuits with negative resistance, they become complementary arcs outside the 2D chart and complementary semi-circles in the south hemisphere (Asavei et al., 2020). In that usage, the phrase denotes a geometric visualization framework for $0.383$9, impedance, and reflection coefficient, not a quantum probe circuit.
A separate Helmholtz Association report develops a quality indicator for research data and research software publications through a multi-step architecture of dimensions, attributes, maturity levels, weighted aggregation, and radar plots, but it does not use “Quality Indicator Circuits” as a formal acronym (Castell et al., 2024). In coding theory, the acronym SC-QIC refers to serial concatenation of quadratic interleaved codes, a turbo-code structure employing quadratic interleavers in semi-femtocell MIMO systems, again unrelated to quantum layout selection (Rahimian et al., 2017).
In current quantum-computing usage, however, QICs refer specifically to small, structure-preserving probe circuits with known ideal outcomes, used for lightweight, real-time evaluation of candidate layouts on noisy hardware (Srivastava et al., 23 Sep 2025). That definition captures both the technical novelty and the principal limitation of the concept: QICs do not eliminate layout noise, but they provide a circuit-specific mechanism for selecting less noisy regions of the device without incurring the full cost of global characterization.
