Posit Arithmetic Quire: A Precise Accumulator

• Posit arithmetic quire is a wide fixed-point, two’s-complement accumulator that achieves exact, deferred-rounding accumulation of products or quotients.
• It supports fused operations like multiply-add and divide-subtract, enabling precise dot-product and inner-product computations in scientific applications.
• Hardware implementations in platforms like CLARINET and PERCIVAL show significant MSE improvements over IEEE-754 with manageable increases in resource usage.

A posit arithmetic quire is a wide, fixed-point, two’s-complement accumulator that enables exact, unrounded accumulation of products or quotients of posit numbers, with final rounding deferred to the end of the computation. Designed to address the rounding and loss-of-significance pitfalls of fused multiply-add (FMA) in floating-point arithmetic, the quire is integral to the posit arithmetic paradigm. It has been implemented in several hardware architectures and RISC-V cores, most notably CLARINET, Melodica, and PERCIVAL, and evaluated in scientific, linear algebra, and deep learning workloads (Sharma et al., 2020, Mallasén et al., 2021, Mallasén et al., 2023). The posit quire achieves exact dot-product and inner-product accumulation for workloads whose sum-of-squares fits within its extremely wide dynamic range, at considerable—but tractable—hardware cost.

1. Formal Definition and Internal Representation

The quire’s primary function is to enable exact, unrounded accumulation of products or quotients of $N$-bit posit numbers. It is defined as a two’s-complement, fixed-point register of width $Q = 16N$ bits for posit arithmetic as standardized and adopted in modern architectures (Mallasén et al., 2021, Mallasén et al., 2023). CLARINET formally specifies $Q = N^2/2$ bits (Sharma et al., 2020), which coincides with $Q = 16N$ for the canonical values used in most hardware ($N=32,64$).

The internal structure of the quire includes:

• A single $Q$-bit two’s-complement register.
• Products of posit values are aligned as fixed-point integers and accumulated exactly.
• The accumulator maintains the full dynamic range of the sum of posit products; regime and exponent fields are handled during decode/align, not during accumulation (Sharma et al., 2020, Mallasén et al., 2023).
• After accumulation, the quire contents are normalized, encoded, and rounded back to an $N$-bit posit.

For posit parameters $N$ (bit width) and $es$ (maximum exponent size), the quire can represent the full range of possible products of two $N$-bit posits, deferred rounding ensures the final result is minimally affected by rounding error (Mallasén et al., 2023).

2. Supported Fused Operations and Arithmetic Semantics

The quire supports a set of atomic fused operations, corresponding to precise, deferred-rounding accumulation semantics. Melodica and PERCIVAL incorporate at least the following instructions:

• Fused Multiply-Add: $q \leftarrow q + (a \times b)$
• Fused Multiply-Subtract: $q \leftarrow q - (a \times b)$
• Fused Divide-Add: $q \leftarrow q + (a \div b)$
• Fused Divide-Subtract: $q \leftarrow q - (a \div b)$
• Negation and clearing of the accumulator
• Final rounding and conversion from quire to posit (e.g., QROUND or FCVT.P.R)

A sequence of such operations allows for exact accumulation of dot products, matrix multiplications, and iterative solvers before a final rounding and conversion to the native posit format. Instruction-level integration is provided in RISC-V extensions (e.g., Xposit custom opcodes) with specific instructions for quire initialization (QCLR), negation (QNEG), fused MAC (QMADD, QMSUB), and rounding (QROUND) (Mallasén et al., 2021).

3. Microarchitectural Realizations

Multiple hardware implementations have fully realized the quire within RISC-V cores:

• CLARINET/Melodica: Quire is implemented as a $Q$-bit segmented register, with each segment processed in a pipelined adder chain. For $N=32$, $Q=512$ bits (16 segments), for $N=64$, $Q=1024$ bits (32 segments). Leading-zero detection, segmentation, and handshake logic facilitate non-blocking accumulates and fast readout (Sharma et al., 2020).
• PERCIVAL (32): The Posit Arithmetic Unit (PAU) integrates a 512-bit quire alongside integer ALU and FPU, with independent register files and scoreboard logic to manage out-of-order completion. All quire instructions use custom opcodes on RISC-V, with multi-cycle operation for add/subtract and fused multiply-add/subtract (Mallasén et al., 2021).
• Big-PERCIVAL (64): Extends PAU to a 1024-bit quire register, accessible through the same set of RISC-V instructions. Synthesized in both FPGA and ASIC, the PAU+quire is shown to have roughly triple the LUT/area and quadruple the power consumption of a standard double-precision FPU, but incurs no performance penalty for large dot-products and inner-product kernels (Mallasén et al., 2023).

4. Quantitative Comparison to IEEE-754 Floating-Point Accumulation

A posit quire calculator maintains exact intermediate sums during dot product or GEMM operations, performing a single rounding at readout. By contrast, IEEE-754 FMA chains accumulate rounding error at each multiplication-addition step, leading to $O(n)$ ulp total error in $n$-term dot-products.

Quantitative outcomes:

• For 256×256 GEMM with uniformly random inputs, posit32+quire achieves mean-square error (MSE) up to $4$ orders of magnitude lower than IEEE float32 FMADD (MSE ≈ $1.94 \times 10^{-16}$ for posit32+quire vs. $2.36 \times 10^{-12}$ for float32 FMADD) (Mallasén et al., 2021).
• In PolyBench and scientific workloads, posit64+quire attains MSE of $10^{-4} \ldots 10^{-6}$, versus $10^{0} \ldots 10^{-3}$ for IEEE-754 doubles, and delivers up to two orders of magnitude improvement in max-absolute-error and 10–20% fewer iterations for conjugate gradient and biconjugate gradient solvers (Mallasén et al., 2023).
• For large accumulations ($n \gg N$), the quire’s dynamic range allows for accumulation of up to $10^{300}$ terms with no loss of significant digits (Mallasén et al., 2023).

Table: GEMM Kernel Accuracy (MSE vs IEEE 64-bit Gold Standard)

Numeric Format	256×256 GEMM MSE	PolyBench MSE
IEEE float32+FMADD	$\sim 2.36 \times 10^{-12}$	$10^{0} \ldots 10^{-3}$
Posit32+quire	$\sim 1.94 \times 10^{-16}$	$10^{-4} \ldots 10^{-6}$
Posit64+quire	$< 10^{-6}$	$10^{-4} \ldots 10^{-6}$
IEEE float64	Not listed	$10^{0} \ldots 10^{-3}$

5. Hardware Cost and Synthesis Results

The major trade-off in quire implementation is hardware cost and area. Synthesis results across tested platforms include:

• FPGA (Xilinx Kintex-7, 32-bit posit): PAU with 512-bit quire requires an extra 15.7k LUTs over baseline, while the quire’s MAC+rounding itself consumes about 6.5k LUTs. For N=32, quire alone can be 94% of MELodica’s total LUTs (Mallasén et al., 2021, Sharma et al., 2020).
• ASIC (TSMC 45nm/28nm): Posit32+quire uses 76.9k μm² and 67.7 mW, 2.5× the area and power of float32 FPU. Posit64+quire (1024-bit) uses 114,695 μm² and 3.516 mW, ≈3× area and ≈4× power relative to double-FPU (Mallasén et al., 2021, Mallasén et al., 2023).
• The cost of the quire grows quadratically with posit width ($Q \sim N^2/2$), implying a substantial area/power increase for 64-bit designs (Sharma et al., 2020, Mallasén et al., 2023).

6. Performance Characteristics and Best Practices

Performance is highly dependent on kernel structure and quire pipeline utilization:

• For kernels with deep accumulations (GEMM, xDOT, PolyBench), posit32 and posit64 with quire match or slightly outperform IEEE-754 float32 and double for large $n$, due to pipeline hiding and batch accumulation (Mallasén et al., 2021, Sharma et al., 2020, Mallasén et al., 2023).
• For shallow or small-loop accumulations (e.g., Givens rotations), quire latency cannot be effectively hidden; IEEE float FMA may outperform in wall-clock cycles.
• Tiling and blocking strategies in GEMM or matrix factorization can be adjusted to minimize quire rounds and maximize register reuse. For non-tiled GEMM, overhead due to QROUND can be up to 2×; with moderate block sizes, parity with float64 FPU is restored (Mallasén et al., 2023).
• The optimal $(N,es)$ configuration should balance accuracy requirements and hardware constraints; smaller $N$ reduces area and power at modest penalty to accuracy (Sharma et al., 2020).
• For large $Q$, segmentation and pipeline unrolling can be leveraged to manage adder fan-in/fan-out and maintain clock rates (Sharma et al., 2020).

7. Research Applications and Future Directions

The posit quire underpins applications requiring exact inner-product accumulation, such as scientific simulations, iterative solvers, and deep learning. The hardware platforms PERCIVAL, CLARINET, and Big-PERCIVAL provide open-source/reference implementations that expose quire-backed posit instructions in the RISC-V ISA (Mallasén et al., 2021, Sharma et al., 2020, Mallasén et al., 2023).

Adoption in scientific computing has demonstrated:

• Dramatic MSE/max-absolute-error improvement for critical workloads.
• Fewer iterations to solver convergence in Krylov and domain decomposition methods.
• The potential for posit arithmetic with quire to substitute, or even outperform, IEEE floating-point double precision in error-sensitive kernels—at the expense of 2–4× higher logic and energy consumption.

Areas identified for future investigation include:

• Hierarchical, hybrid, or dynamically-configurable quire registers to improve efficiency for small-to-medium kernels.
• Compiler and codegen improvements to treat posit+quire as native types and minimize instruction overhead.
• Hardware support for quire-side non-linear operations (square-root etc.), required by QR and Givens factorization routines (Sharma et al., 2020).

A plausible implication is that, for large-scale, ill-conditioned, or error-propagation-sensitive computations, posit arithmetic with quire may offer a compelling alternative to conventional floating-point, provided hardware resources allow for the increased area and power budget.