Quire-Powered Accumulators for Exact Dot-Products

• Quire-powered accumulators are fixed-point fused multiply-accumulate registers within posit arithmetic that enable exact dot-product computations by deferring rounding until after full accumulation.
• They are integrated into hardware systems like PERCIVAL and Big-PERCIVAL, achieving one fused MAC per cycle while managing extensive data widths via a single, wide two’s-complement register.
• Empirical studies show these accumulators reduce mean-squared errors by up to 4 orders of magnitude and lower iteration counts in numerical methods, critical for scientific computing.

A quire-powered accumulator is a fixed-point fused multiply-accumulate (FMA) register designed for posit arithmetic systems. It enables the exact, intermediate-rounding-free summation of large sequences of products, allowing hardware computation of dot-products and similar reductions with minimal accumulated numerical error. In posit-$n$ arithmetic, the quire is a $16n$-bit two’s-complement accumulator which can hold the exact sum of up to $2^{31}-1$ products for $n=64$, and $2^{31}-1$ for $n=32$ (Mallasén et al., 2023, Mallasén et al., 2021). After all products are accumulated, a single rounding operation converts the quire contents to a standard posit value. This approach provides significant improvements in dynamic range and accuracy over traditional floating-point FMA or pairwise summation, with critical implications for scientific computing workloads.

1. Quire Register Architecture and Mathematical Properties

The posit standard defines the quire (“exact dot-product accumulator”) as a fixed-point integer register of width $16n$ bits for $n$-bit posits (e.g., 1024 bits for posit64, 512 bits for posit32). The quire register, denoted $Q$, follows two’s-complement arithmetic. There is no segmentation or banked structure; $Q$ is managed as a single wide accumulator, typically implemented as an array of wide words (64/128 bits).

For a sequence of input pairs $a_i, b_i \in \mathrm{Posit}_n$, the fused multiply-accumulate operation is:

$Q \leftarrow Q + a_i \cdot b_i$

After $k$ products, the final posit is obtained by rounding:

$P = \mathrm{round}_{\mathrm{Posit}_n}(Q)$

The posit fields (sign, regime, exponent, fraction) are extracted from $Q$’s two’s-complement representation, allowing for correct regime and exponent calculation from the integer bit-length. For posit64, the exact sum can be maintained for $2^{31}$ individual products without loss.

This scheme prevents intermediate rounding, offering true “exact dot-products.” The rounding, including guard/round/sticky bits, occurs only after the full accumulation.

2. Hardware Integration and Instruction Set Architecture

In implementations such as Big-PERCIVAL (posit64) and PERCIVAL (posit32), the quire is integrated into the pipeline via a specialized Posit Arithmetic Unit (PAU) in the EX stage of a CVA6 RISC-V core. This involves:

• Single 1024-bit (posit64) or 512-bit (posit32) quire register.
• Extended PAU supporting posit add, sub, mul, div, sqrt, quire MAC (Q ← Q + a·b), and quire control (clear, negate, round).
• Dedicated instructions in the Xposit custom opcode space, for example:
  • QMADD.S rd, rs1, rs2 (Q ← Q + (rs1 * rs2))
  • QMSUB.S (Q ← Q – (rs1 * rs2))
  • QCLR.S (Q ← 0)
  • QNEG.S (Q ← –Q)
  • QROUND.S rd (rd ← Q→Posit)

The EX stage handles the enlarged datapath to transfer the quire register efficiently. The quire pipeline is split across registers, achieving one fused MAC per cycle and matching the throughput of a 64×64-bit multiplier (posit64 case) (Mallasén et al., 2023).

No provision is made for quire register spill/fill to memory (QLOAD/QSTORE) in current hardware; the quire is strictly internal, and any multitasking or save/restore must be managed in software (Mallasén et al., 2021).

3. Hardware Cost, Area, and Power Overheads

Quire integration is hardware-intensive due to the high register width. Empirical synthesis results (FPGA and ASIC) quantify these costs:

Implementation	Area Increase	Power Increase	Additional LUTs/FFs
Big-PERCIVAL (posit64+quire)	+43,605 μm²	+1.558 mW	+9,834 LUTs, 1,909 FFs (quire-MAC only)
PERCIVAL (posit32+quire)	+36,445 μm²	+30.11 mW	+6,500 LUTs, 1,600 FFs (Kintex-7)

For example, the total area for a 32-bit Posit PAU with quire is 76,970 μm² at 45 nm (PERCIVAL), compared to 40,525 μm² without quire and 30,691 μm² for a standard IEEE-754 FPU (Mallasén et al., 2021). In Big-PERCIVAL (64-bit), the quire consumes approximately 50% of the Posit Arithmetic Unit’s LUT resources on FPGA (29,781 LUTs for full PAU with quire, versus 71,090 μm² area for PAU-only in ASIC) (Mallasén et al., 2023).

Pipeline latency for the quire-MAC is fully amortized after initial fill; QROUND (1024→64 bits) incurs ~5 cycles of latency, while QCLR and QNEG require 1 cycle.

4. Numerical Accuracy and Performance Characteristics

Quire-powered accumulation yields substantial numerical precision benefits in dot-product-heavy numerical kernels:

• GEMM benchmarks (PolyBench, DNN max-pool layers) show mean-squared-error (MSE) reductions of up to 4 orders of magnitude versus IEEE-754 float32 and double precision (Mallasén et al., 2023, Mallasén et al., 2021).
• Posit64+quire: Up to $10^{-4}$ times the MSE of doubles, max absolute error up to $10^{-3}$ lower (Mallasén et al., 2023).
• Posit32+quire: MSEs as low as $1.14 \times 10^{-17}$ (16×16 GEMM) versus $1.49 \times 10^{-14}$ for float32 with FMADD (Mallasén et al., 2021).
• Significant iteration count reductions seen in conjugate-gradient and biconjugate-gradient solvers (up to 20% fewer iterations in BiCG for unsymmetric matrices).

Timing analysis demonstrates the throughput of posit32/64 quire accumulators is on par with float32 FMADD for large kernels; the bottleneck shifts to dataflow and loop overhead. There is no performance penalty versus single-precision floats; posit32 with quire is 1.3–1.7× faster than float64 due to lower per-operation cost. Max-pooling operations with posit32 experience no slowdown versus float32, as no quire is involved (Mallasén et al., 2021).

5. Design Trade-Offs and Limitations

The primary constraint is hardware resource and power consumption, with the quire accounting for approximately 50% of total area for the posit arithmetic unit at $n=64$ and a substantial increment for $n=32$ as well. For size- or power-restricted systems, quire instantiation can be parameterized or omitted entirely.

Operation ordering is constrained: all fused multiply-accumulates intended for a single “exact” result must be processed consecutively in the same quire prior to rounding, which restricts loop reordering in matrix multiplications (e.g., classic $i-k-j$ GEMM forms are disallowed). Tiled GEMM and block-dot algorithms ameliorate this by ensuring each output element’s partial sum is handled in a single quire sequence (Mallasén et al., 2023).

The accumulation range is determined by register width: $2^{31}$ products for both posit32 (512-bit Q) and posit64 (1024-bit Q). Explicit quire clearing is mandatory when switching between independent dot-products.

6. Architectural and Algorithmic Insights

From a hardware perspective, recommended practices for high-performance quire accumulators include:

• Full pipelining of the fused MAC operations (multiply and wide add).
• Multiport, word-indexed register banks to minimize pipeline stalls.
• Parameterization of quire width ($n \cdot k$, $k < 16$ for small posits) if the full $2^{31}$ product headroom is unnecessary.
• Use of Mitchell-style logarithmic approximate division and square root units to reduce area and power when tolerance allows (error ≤ 11.11%) (Mallasén et al., 2021).

On the algorithmic side, code restructuring is essential to maximize quire benefit:

• Load and accumulate each output (e.g., $C[i,j]$ in GEMM) in a quire in a continuous run, then round before proceeding.
• Employ cache blocking (tile size $\gtrsim 16$) to hide QROUND latency.
• In kernels not adhering to the quire FMA pattern (e.g., streaming, stencil), disable quire accumulation.
• For iterative solvers, inner products benefit maximally from quire-powered accumulation, whereas outer updates may use standard posit arithmetic (Mallasén et al., 2023).

A plausible implication is that wider or banked quires may be advantageous where multiple, independent dot-products must be accumulated in parallel, but current implementations restrict to a single internal register for area efficiency.

7. Context within Scientific Computing and Recommendations

Quire-powered accumulators bridge the gap between the accuracy demands of scientific computing and the efficiency constraints of low-precision arithmetic. In large-scale linear algebra, iterative solvers, and DNNs, the quire achieves “exact” dot-product accumulation in hardware, greatly reducing error propagation and iteration counts without increasing memory bandwidth (Mallasén et al., 2023, Mallasén et al., 2021).

Hardware area and power overheads are substantial, justifying selective deployment only to kernels critically affected by numerical error in reductions. Algorithmic modifications, as well as hardware parameterization and approximate functional units, are practical measures to enhance system-wide tractability.

The integration of the quire into the PERCIVAL and Big-PERCIVAL cores demonstrates the practical feasibility and scientific utility of this approach. The quire’s contribution to ensuring robust, high-precision reductions makes it a compelling feature—especially for workloads where the full dynamic range and accuracy of IEEE 754 doubles are insufficient or too costly in area and bandwidth.