Physically-Aware Preemptive Virtual Channels

• The paper introduces a deadlock-free scheme that statically binds AXI4 ReadData and WriteData flits to two dedicated virtual channels, eliminating protocol-level circular waits.
• The design leverages a single 512-bit wide data plane augmented with minimal handshake signals, reducing the area and control overhead compared to multiplane architectures.
• Implementation results show competitive timing (1.70 GHz) and a 43% reduction in metal-track usage, preserving performance without deep buffering or complex dynamic allocation.

Searching arXiv for the specified papers and closely related work to ground the article. I’ll look up the cited arXiv records for verification and context. Physically-Aware Preemptive Virtual Channels are a deadlock-free AXI4 traffic-class separation scheme for wide-link Networks-on-Chip in which read-data and write-data flits are statically bound to two virtual channels on a shared physical data link, and output-link ownership is forcibly relinquished when downstream readiness changes, so that protocol-level circular waits are eliminated without duplicating the wide plane or introducing the full control complexity of conventional virtual-channel routers (Leone et al., 1 Jul 2026). The design is motivated by a specific modern NoC trade-off: multiplane fabrics avoid inter-class dependencies by replication of physical links, whereas classical VC routers typically incur substantial control, buffering, area, and timing overhead. The physically-aware aspect of the scheme lies in treating the 512 bit data plane as the dominant physical resource and preserving it as a single plane augmented only with per-VC handshake signals.

1. Problem setting and design objective

In AXI4 many-core Systems-on-Chip, deadlock freedom is not guaranteed by routing alone. The central observation is that protocol-level dependencies between read and write traffic can create circular waits at the network endpoints, even when the routing algorithm itself is deadlock-free. The 2026 work evaluates four AXI4 traffic-class separation schemes—a multiplane baseline and three lightweight VC-based designs—and positions Preemptive-VC as a way to retain deadlock freedom while avoiding the link duplication of multiplane NoCs and the control overhead of conventional VC routers (Leone et al., 1 Jul 2026).

The problem is especially acute in wide-link NoCs intended to sustain high memory bandwidth. Decoupling traffic classes is known to avoid the endpoint dependency cycle, but the implementation cost differs sharply across approaches. A multiplane solution duplicates wide physical links and increases routing pressure. A conventional VC router, by contrast, introduces dynamic VC-management machinery and associated timing and area costs. Preemptive-VC addresses this by using only two virtual channels on the wide data link, preserving single-cycle behavior and reusing the existing 512 bit physical link.

A common misconception is that deadlock-free routing in the network core is sufficient for AXI4 deadlock freedom. The cited work explicitly rejects that assumption: the deadlock cycle can arise at the protocol level, at endpoints such as a DMA, from the interaction between AXI4 read and write channels rather than from the topology or routing function alone.

2. Router microarchitecture

The Preemptive-VC datapath assigns two registered virtual channels to each wide output port. VC₀ is bound to AXI4 ReadData flits, or R beats, and VC₁ is bound to AXI4 WriteData flits, or W beats. Each VC is backed by a 1-flit deep FIFO at the network-interface source side. The router preserves FlooNoC’s single-cycle narrow request/response planes and the wide data plane, and uses a 5×5 crossbar switch replicated for each physical plane (Leone et al., 1 Jul 2026).

A defining architectural choice is the absence of dynamic VA. The design does not perform dynamic virtual-channel allocation; accordingly, it removes the bulk of the classical 4-stage VC router logic, including dynamic credit allocation and per-flit routing-to-VC remapping. The remaining control structure is a small round-robin arbiter with preemption logic. In each cycle, that arbiter grants the shared physical link to one VC whose downstream ready signal is high.

The wide data plane carries the handshake set $\{valid_0, ready_0, valid_1, ready_1\}$ in addition to the 512 bit data bus, for a total of 516 wires. The ready signals are registered before feeding back into the arbiter, so that no combinational ready-to-valid path spans two routers. At run time, the arbiter samples $(valid_0^n, valid_1^n)$ together with the registered downstream $(ready_0^n, ready_1^n)$ and grants access according to round-robin fairness. If downstream readiness disappears, preemption occurs after the current cycle rather than through a combinational freeze of the link.

This organization is the basis of what the paper calls a “speculative valid + preempt” mechanism. In the paper’s formulation, that mechanism breaks Coffman’s no-preemption condition while maintaining non-combinational link control and limiting buffering to one flit per VC.

3. Deadlock model and formal argument

The formal deadlock argument is expressed through a channel dependency graph. The relevant AXI4 channel set is $C=\{AW,W,B,AR,R\}$. The protocol-level deadlock arises because an endpoint can issue $AR \rightarrow R$, immediately repurpose those $R$ flits into new $AW/W$ pairs, and on the same physical plane starve incoming write bursts. The dependency cycle is written as

$$AR \rightarrow R \rightarrow \{crossbar\} \rightarrow AW \rightarrow W \rightarrow \{back\ to\ AR\}.$$

This is the cycle that the architecture is designed to remove (Leone et al., 1 Jul 2026).

Preemptive-VC lifts the analysis to the VC level with $C'=\{C_0,C_1\}$, where $C_0$ carries R flits and $(valid_0^n, valid_1^n)$0 carries W flits. The paper’s Lemma 1 states that the VC-level dependency graph has no edges $(valid_0^n, valid_1^n)$1 or $(valid_0^n, valid_1^n)$2 at the shared output resource. The reason is operational rather than merely classificatory: a flit may hold the link at cycle $(valid_0^n, valid_1^n)$3 only if its corresponding downstream ready was asserted at $(valid_0^n, valid_1^n)$4, and if that ready signal drops, the arbiter preempts that VC at $(valid_0^n, valid_1^n)$5, immediately granting the link to the other VC if it is valid.

The resulting dependency graph contains only self-loops $(valid_0^n, valid_1^n)$6 and $(valid_0^n, valid_1^n)$7. In the paper’s statement, such self-loops “cannot cause a cycle involving two or more classes,” so the graph is acyclic across classes. The proof emphasizes that hold-and-wait across VCs cannot persist over multiple cycles because the shared link is released immediately upon preemption; the only waiting occurs at the source FIFO.

The significance of the proof is that deadlock freedom is obtained without dynamic allocation or deep buffering. The logical separation of traffic classes is thus coupled directly to a time-domain preemption rule at the shared physical link.

4. Physical cost model, implementation, and measured overheads

The physically-aware character of the design appears most clearly in implementation. All four schemes—Multiplane, Naive VC, Credit-Based VC, and Preemptive-VC—were implemented in FlooNoC, and two routers were placed and routed at 750 $(valid_0^n, valid_1^n)$8m distance in TSMC 7 nm under SS/$(valid_0^n, valid_1^n)$9 conditions (Leone et al., 1 Jul 2026). The evaluation reports bandwidth utilization, area in kGE, maximum frequency in GHz, and tile-boundary metal-track usage.

Configuration	Area / Max Freq	Metal Tracks
Multiplane (2×512 b)	270 kGE / 1.68 GHz	2776
Naive VC	275 kGE / 1.42 GHz	1578
Credit-Based (3-buff)	345 kGE / 1.62 GHz	1610
Preemptive-VC	279 kGE / 1.70 GHz	1578

All four entries are reported with 100% bandwidth utilization in the implementation table. Relative to Multiplane, Preemptive-VC reuses the single 512 bit plane plus four extra valid/ready wires, yielding 1578 metal tracks instead of 2776. The paper computes

$(ready_0^n, ready_1^n)$0

of the extra wide-plane resources saved compared to Multiplane. It further states that because the wide plane originally accounts for approximately 78% of tile-boundary wiring, this corresponds to up to 78% of link resources saved versus the pure Multiplane design. The abstract reports the same qualitative conclusion as “up to 76% of link resources,” which indicates that the headline saving is consistently presented as a large reduction in link-resource cost, even though different sections of the paper use slightly different summary figures.

Area grows from 270 kGE to 279 kGE, which the paper reports as 3%, and timing is restored to 1.70 GHz versus 1.68 GHz for the multiplane baseline. By contrast, Naive VC reaches 1.42 GHz, or 15% below baseline, and Credit-Based VC reaches 345 kGE, or 28% above baseline. The implementation evidence therefore characterizes Preemptive-VC as a design that retains the wiring footprint of a single-plane network while avoiding the major timing loss of Naive VC and the area increase of deeper credit-based buffering.

5. Cycle-accurate behavior in a 4×4 Snitch mesh

System-level evaluation was performed by integrating the router variants into a 4×4 mesh SoC of Snitch clusters and running a cycle-accurate DMA-broadcast microbenchmark in QuestaSim 2023.4. Each tile receives a 2D-broadcast of $(ready_0^n, ready_1^n)$1-beat bursts through a binary-tree fanout. The reported metric is wall-clock cycles as a function of burst size $(ready_0^n, ready_1^n)$2 (Leone et al., 1 Jul 2026).

In that experiment, all but the 2-buffer Credit-Based design track the Multiplane baseline exactly. The 2-buffer Credit-Based version exhibits a 33% throughput shortfall, attributed to having only a 2-flit FIFO instead of 3, and this produces approximately 1.5× longer runtimes for large $(ready_0^n, ready_1^n)$3. Neither Naive-VC nor Preemptive-VC incur a performance penalty in the reported setup.

The specific interpretation given in the paper is that one-flit buffering plus preemption is sufficient to hide backpressure latency on the wide plane. This is important because it ties the deadlock argument to an implementation result: preemption is not merely a correctness device but also a mechanism that preserves full single-cycle link utilization under the evaluated workload.

The broader design implication is that traffic-class separation need not imply either duplicated wide links or deep buffering. In the measured 4×4 AXI4 mesh, the lightweight preemptive mechanism attains the same observed runtime behavior as the more physically expensive multiplane baseline.

6. Relation to earlier “preemptive” and “virtual channel” formulations

An earlier, unrelated use of closely related terminology appears in wireless communication research on reconfigurable antennas. There, each antenna mode induces a virtual channel represented by a pair $(ready_0^n, ready_1^n)$4, where $(ready_0^n, ready_1^n)$5 is a Markov transition matrix and $(ready_0^n, ready_1^n)$6 is a per-state erasure profile. The action set is $(ready_0^n, ready_1^n)$7, where $(ready_0^n, ready_1^n)$8 denotes “switch antenna (preempt)” and $(ready_0^n, ready_1^n)$9 denotes transmission in virtual channel $C=\{AW,W,B,AR,R\}$0 (Kumar et al., 2012).

That formulation is explicitly built as an MDP and, under partial observability, as a POMDP on belief states. Its Bellman equation is

$C=\{AW,W,B,AR,R\}$1

with throughput and delay defined respectively by a long-run average throughput $C=\{AW,W,B,AR,R\}$2 and an average delay $C=\{AW,W,B,AR,R\}$3 derived via Little’s law. The paper states that for moderate-to-high channel memory, a preemptive switching policy can significantly outperform a fixed-antenna baseline in throughput and mean waiting time.

The NoC use of Physically-Aware Preemptive Virtual Channels is different in domain, mechanism, and objective. In the 2012 wireless setting, “virtual channel” refers to a channel induced by an antenna radiation pattern and “preemption” suspends transmission for one codeword interval while switching modes. In the 2026 AXI4 NoC setting, the virtual channels are statically bound traffic classes on a shared physical output link, and preemption refers to immediate relinquishing of that link when downstream readiness changes. This suggests a shared scheduling vocabulary across communication subfields, but not a shared resource model or control problem.

The distinction matters because the 2026 contribution is not a generic theory of preemptive virtual channels. It is a physically-aware NoC architecture for deadlock-free AXI4 meshes, grounded in a specific wide-link cost model, a specific static mapping of R and W flits to VC₀ and VC₁, and a specific preemption rule that removes cross-class hold-and-wait at the output resource.