Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip

Abstract: As many-core Systems-on-Chip (SoCs) continue to scale, Networks-on-Chip (NoCs) must sustain increasingly high memory bandwidth while preserving deadlock freedom. In AXI4 systems, protocol-level dependencies between read and write traffic can create circular waits at the network endpoints, even when the routing algorithm itself is deadlock-free. Decoupling these traffic classes avoids such dependencies, but exposes a key implementation trade-off: multiplane NoCs duplicate wide physical links and increase routing pressure, whereas conventional Virtual Channel (VC) routers add substantial control complexity, area, and timing overhead. This work revisits this trade-off for modern wide-link NoCs. We evaluate four deadlock-free AXI4 traffic-class separation schemes: a multiplane baseline and three lightweight VC-based designs. Among these designs, we propose Preemptive VCs, a physically-aware architecture that can save up to 76% of link resources with comparable frequency and only 3% router area overhead relative to the multiplane design.

• The paper demonstrates that the preemptive VC architecture attains deadlock freedom in AXI4-based NoCs while matching multiplane performance.
• It introduces round-robin link arbitration with preemption to decouple read/write traffic, reducing timing overhead and maintaining high operating frequency.
• Experimental evaluation on a 4×4 mesh SoC shows full bandwidth utilization, just 3% area overhead, and a 76% reduction in routing resource usage compared to multiplane.

Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip

Introduction

This paper addresses a central challenge in AXI4-based Network-on-Chip (NoC) systems: achieving protocol-level deadlock freedom in the presence of high-throughput, wide-link interconnects for modern many-core SoCs. The interaction between AXI4 protocol dependencies and wormhole routing can induce deadlocks at network endpoints, even with deadlock-free routing algorithms. Historically, protocol-level deadlock avoidance in NoCs has revolved around a trade-off between multiplane architectures, which physically separate traffic classes but incur significant routing overhead, and Virtual Channels (VCs), which share links at the expense of area and control complexity. The authors revisit this trade-off in the context of modern wide-link NoCs and propose a novel Preemptive VC architecture which achieves efficient traffic decoupling, minimal area overhead, and strongly reduced routing resource usage.

Background and Problem Context

Strict AXI4 protocol compliance at NoC endpoints is mandated by system integration requirements, but exposes circular wait dependencies between read and write traffic. Classical solutions include multiplane NoCs—duplicating wide physical links for each class—and full-fledged VC routers, classically built for dynamic traffic mapping and improved link utilization. However, classical VCs impose significant timing and area overhead due to per-VC buffers and control logic, making multiplanes the pragmatic industry choice despite their routing cost, especially as link widths increase into the kilobit regime.

Recent scaling trends in accelerator-centric SoCs—incorporating hundreds of thousands of AI cores, as in wafer-scale arrays—are driving on-chip bandwidth requirements to multi-petabyte/s levels. This shift necessitates ultra-wide NoC links, substantially amplifying the physical and routing resource penalties incurred by multiplane replication. Simultaneously, existing work such as FlooNoC demonstrates the feasibility and challenges of open-source, AXI4-compliant, high-throughput NoC fabrics operating at up to 1024-bit links.

Architectures for Deadlock-Free AXI4 Traffic Separation

The paper systematically explores four deadlock-free NoC router architectures for AXI4 traffic separation, targeting the decoupling of read and write channels to break protocol-level circular dependencies:

1. Multiplane Baseline: Physically separates wide data links for read and write channels, eliminating class contention at cost of doubled routing width and area. This serves as the reference point for resource and frequency comparisons.
2. Naive VC Implementation: Employs VC separation using replicated valid/ready signaling but introduces a combinational ready-to-valid dependency across the link. This manifests as a critical path spanning twice the tile width, significantly degrading attainable operating frequency.
3. Credit-Based VC: Removes combinatorial dependencies by adopting credit-based flow control, with per-VC credit counters managing buffer occupancy. While restoring frequency, the pipelined return of credits necessitates deeper FIFOs (≥3 entries per VC) to avoid throughput loss. Shallower buffers result in up to 33% reduced bandwidth utilization.
4. Preemptive VC (Proposed): Introduces round-robin link arbitration among VCs, with preemption enabled if the active VC cannot progress (downstream not ready). The downstream ready is registered, removing long combinational paths; preempted transactions remain buffered at the source, and arbitration immediately grants the link to alternative ready VCs. Achieves full bandwidth utilization and timing parity with multiplane, with minimal area (3% overhead over multiplane) and a substantial 76% reduction in routing resource usage.

(Figure 1)

Figure 1: a) AT plots of the analyzed deadlock-free designs. b) Area breakdown at $\SI{1.1}{\text{GHz}}$. c) Routing usage relative to baseline.

Evaluation and Results

The architectural explorations are integrated and evaluated within a $4 \times 4$ mesh SoC containing Snitch compute clusters interconnected by FlooNoC variants. Performance measurements utilize cycle-accurate simulation, and physical realization leverages TSMC 7nm P&R targeting realistic tile-to-tile distances.

• Performance: All designs except for the under-buffered (2-entry) Credit-Based VC achieve identical bandwidth utilization and effective application throughput as multiplane. The 2-entry Credit-Based scheme exhibits the expected 33% throughput deficit.
• Timing: The multiplane and Preemptive VC achieve the highest feasible frequencies ($\sim$1.7 GHz). The Naive VC is bottlenecked by extended critical paths (down to 1.42 GHz), while Credit-Based VC restores timing but at considerable area cost due to required buffer capacity.
• Area and Routing: The multiplane design inflates routing track requirements by 76% (doubling link width), with a corresponding area increase. Preemptive VC matches multiplane frequency, with only 3% area overhead, but achieves this with nearly baseline routing resource usage (increasing by just 1%). The minimal extra hardware in Preemptive VC is attributed to arbitration and ready-masking.

Implications and Future Perspectives

The study demonstrates that with a physically-aware VC architecture explicitly tailored for static, protocol-driven traffic-class separation (as opposed to dynamic VC allocation for general link utilization), the resource trade-off for protocol-deadlock freedom fundamentally shifts. The Preemptive VC scheme enables large-scale many-core designs to simultaneously achieve:

• AXI4-compliant, deadlock-free NoC connectivity;
• Preserved achievable operating frequency even for wide, high-bandwidth links;
• Robust area/resource efficiency, eliminating the previous necessity to duplicate costly wide routing fabrics.

This enables greater scalability for emerging wafer-scale and accelerator-centric SoC applications, where the physical cost of routing dominates, and area/energy budgets are stringent.

Looking forward, broad adoption of preemptive or otherwise lightweight, statically allocated VC mechanisms are likely as AI and high-performance SoC designers continue to push bandwidth density. The decoupling of protocol constraints from classical, high-overhead VC controllers also opens the door for further architectural integration, deeper compiler-NOC co-design, and more fine-grained power/performance management.

Conclusion

The paper provides a critical reassessment of the multiplane versus VC trade-off for deadlock-free NoCs under modern design constraints. The Preemptive VC approach enables deadlock-free, AXI4-compatible links with minimal area, baseline routing usage, and no degradation in frequency or bandwidth, effectively reconciling previously polarized solutions. As network and accelerator fabrics become increasingly bandwidth- and resource-constrained, practical, physically-aware VC designs will become essential in the evolution of scalable on-chip interconnects.