Photonic SRAM Array

• Photonic SRAM arrays are memory architectures that use micro-ring resonators, waveguides, and photodiodes to implement optical bistable latches.
• They enable ultra-fast, parallel data storage and in-memory computing with demonstrable speeds up to 40 GHz and efficient matrix–vector multiplication.
• Key challenges include managing thermal drift, minimizing waveguide loss, and balancing trade-offs between energy per bit, area, and bandwidth compared to electronic SRAM.

Photonic SRAM (pSRAM) arrays are memory architectures that implement static random access memory principles in the optical domain by using integrated photonic devices such as micro-ring resonators (MRRs), waveguides, and on-chip photodiodes. These arrays exploit high optical bandwidth, minimal capacitive and resistive interconnects, and in situ parallelism, enabling ultra-fast data storage and computation on silicon photonics platforms. pSRAM arrays are central to photonic in-memory computing, offering a fundamental alternative to electronic SRAMs by addressing the physical limitations of electrical signaling at advanced technology nodes (Kaiser et al., 25 Mar 2025, Arockiaraj et al., 31 Jan 2026, Kaiser et al., 28 Jun 2025, Wijeratne et al., 23 Mar 2025, Kudalippalliyalil et al., 2021, Kaiser et al., 28 Jun 2025, Ashtiani, 2024).

1. Bitcell Architecture and Operation

At the core of a pSRAM array is the differential, cross-coupled MRR bitcell. Each cell incorporates two identical micro-ring resonators (M₁, M₂), cross-coupled via differential photodiodes (PDs), forming an optical bistable latch. The associated state (Q, Q̄) is maintained as a voltage across the PD nodes, which in turn modulate the MRRs' resonance to sustain the stored bit via positive-feedback. Light from an input continuous-wave laser at λ₀ is split equally and drives both rings; the resonance state (on or off) of each ring determines the optical pathway, generating differential photocurrents that reinforce or toggle the bistable state (Kaiser et al., 25 Mar 2025).

The through-port and drop-port transfer functions are, respectively:

$$H_{th}(ω) = \frac{t - a e^{-jφ}}{1 - a t e^{-jφ}}, \qquad H_{dr}(ω) = \frac{j κ \sqrt{a} e^{-jφ/2}}{1 - a t e^{-jφ}},$$

where $t$ and $κ$ are the self- and cross-coupling coefficients ($t^2 + κ^2 = 1$), $a$ is the round-trip loss, and $φ(ω)$ is the round-trip phase shift. Bistability is ensured by the cross-coupled feedback, with latch stability governed by a loop-gain condition:

$$|H_{loop}| = |H_{dr,1}(ω)·G_{PD1}·H_{dr,2}(ω)·G_{PD2}| > 1.$$

Integration of differential PDs enables robust voltage swings at the Q node, with the photocurrent given by $I_{pd} = R·P_{in}$, where $R$ is the PD responsivity.

2. Array Organization, Scaling, and Optical Routing

pSRAM arrays are constructed by tiling bitcells in a 2D arrangement, with each row (wordline) driven by a common optical bus, and each column exploiting differential optical (bitline) waveguides. Waveguide crossings are managed via shallow-etch or vertical routing to minimize crosstalk, and shallow-etched trenches provide row isolation (Kaiser et al., 25 Mar 2025). The per-cell footprint is 330 μm × 290 μm using GlobalFoundries 45SPCLO technology, directly affecting the aggregate area:

$$A(N, M) = N·W_{row} × M·W_{col} + (N+1)·L_{bend} + (M+1)·L_c$$

where $N, M$ are array dimensions, $W_{row}$ and $W_{col}$ the pitch, and $L_{bend}$, $L_c$ are waveguide bend and coupling region lengths.

Power budget analysis considers waveguide loss ($α$), required end-point power ($P_{min}$), and path length:

$$P_L[dBm] = P_{min}[dBm] + α·L[cm] + \text{margin}[dB]$$

WDM (wavelength-division multiplexing) and/or time-multiplexing speed optical delivery and addressing across the array (Wijeratne et al., 23 Mar 2025, Kaiser et al., 28 Jun 2025).

3. Read, Write, and Compute Dynamics

pSRAM access leverages the photonic domain's speed:

• Write: An optical pulse ($P_{pulse}$, typically 1 mW) is injected for $t_{wr}$ (∼25–50 ps) along the write bitline. The resulting PD current shifts the bistable latch.
• Read: Sensed by evaluating which MRR is resonant, with the output photodiode and frontend TIA converting optical to voltage swings.
• Latency: Read/write latency ($t_{rd}, t_{wr}$) is dominated by ring photon lifetime ($τ_{ring} = Q/ω_r$), PD response time, and waveguide propagation, yielding speeds up to 40 GHz (∼20–50 ps per access) (Kaiser et al., 25 Mar 2025, Kaiser et al., 28 Jun 2025).
• Energy: Write energy per bit $E_{sw} ≃ P_{pulse}·t_{wr}/η_{wp} ≈ 0.6$ pJ; continuous bias gives static $E_{static} ≈ 0.03$ pJ/bit per period for the GF45SPCLO process (Kaiser et al., 25 Mar 2025).

Large-scale pSRAM arrays permit in-situ parallel computation—specifically, matrix–vector multiplication—by configuring MRRs’ resonance proportional to stored weights. Input vectors encoded optically traverse the array, yielding output currents at the photodiode columns:

$$y_i = \sum_{j=1}^M |H_{ij}(ω)|^2·x_j ≃ \sum_j w_{ij}·x_j$$

This design supports TOPS-class throughput at sub-100 ps latencies (Kaiser et al., 25 Mar 2025, Kaiser et al., 28 Jun 2025, Wijeratne et al., 23 Mar 2025).

4. System-Level Performance and In-Memory Compute

pSRAM arrays have been analyzed via system-level performance models mapping algorithmic workloads (e.g., MTTKRP, Sod shock tube, Vlasov–Maxwell equation) to hardware. For a single-wavelength, 1×256-bit GF45SPCLO pSRAM array, sustained throughputs of 1.5 TOPS (Sod shock tube), 0.9 TOPS (MTTKRP), and 1.3 TOPS (Vlasov–Maxwell) have been reported with 2.5 TOPS/W energy efficiency (Arockiaraj et al., 31 Jan 2026). Critical performance metrics:

• Modulation speed: up to 20–40 GHz per bitcell (Wijeratne et al., 23 Mar 2025, Kaiser et al., 25 Mar 2025).
• Per-bit energy: 0.5–0.8 pJ for write/switch (Kaiser et al., 28 Jun 2025, Arockiaraj et al., 31 Jan 2026).
• MAC array: 16×16, 3-bit weights, 4 wavelengths → 4.1 TOPS, 3.02 TOPS/W (Kaiser et al., 28 Jun 2025).
• Algorithm-to-hardware mapping shows that communication–computation balance and conversion overheads limit scaling at small N (array size), while bandwidth dominates at large N (Arockiaraj et al., 31 Jan 2026).

Wavelength scaling (WDM) across 52 channels enables raw per-bank throughput approaching O(10 PetaOps) in state-of-art designs; the effective number of operations per second is determined by device speed, channel count, and optical/electrical conversion efficiency (Wijeratne et al., 23 Mar 2025).

5. Trade-Offs, Bottlenecks, and Integration Challenges

Key trade-offs include:

• Bandwidth vs. Q-factor: Higher-Q rings provide better selectivity, but limit bandwidth and require tighter thermal control (Kudalippalliyalil et al., 2021, Kaiser et al., 28 Jun 2025).
• Power and area: pSRAM cells are 2–5× larger than advanced electronic SRAMs (e.g., 0.096 mm² pSRAM cell versus 0.05 mm² for 6T e-SRAM at 45 nm) (Kaiser et al., 25 Mar 2025).
• Energy efficiency: pSRAM switching energy is higher than electrical SRAM, but the optical approach removes RC delay and scales better with bandwidth—especially for in-memory computing (Kaiser et al., 25 Mar 2025, Kaiser et al., 28 Jun 2025).

Integration complexity arises from:

• Thermal drift of ring resonators leading to resonance misalignment, addressed by microheaters and feedback (Wijeratne et al., 23 Mar 2025, Kudalippalliyalil et al., 2021).
• Crosstalk and waveguide loss, mitigated through careful layout, passive absorbers, and restricted WDM channel counts (Kaiser et al., 25 Mar 2025, Kudalippalliyalil et al., 2021, Kaiser et al., 28 Jun 2025).
• On-chip ADC area and power, primarily in large-scale parallel arrays (Wijeratne et al., 23 Mar 2025, Kaiser et al., 28 Jun 2025).

6. Advanced Functionality: In-Memory Logic and Hybrid Architectures

Photonic SRAM integration supports compute-in-memory paradigms. Advanced cells such as X-pSRAM include embedded Boolean logic (e.g., in-memory XOR) using MRRs as both data latches and logic gates, extending the functional range to hyperdimensional computing, cryptography, and binary neural networks. These designs attain 10 GHz logic rates and per-XOR energies of 13.2 fJ, with WDM enabling simultaneous multi-bit computation in a single cycle (Kaiser et al., 28 Jun 2025).

Mixed-signal designs incorporating electro-optic ADCs allow rapid analog-to-digital conversion via p-hot encoding; a p-bit ADC based on MRR-thresholding achieves 8 GS/s at 2.32 pJ/conversion (Kaiser et al., 28 Jun 2025).

7. Comparison to Electronic SRAM and Roadmap

pSRAM arrays fundamentally differ from CMOS SRAM by eliminating capacitive and resistive wire delays, enabling direct photonic interconnects and parallelism limited only by device physics, not by RC time constants (Kaiser et al., 25 Mar 2025, Kudalippalliyalil et al., 2021). Although per-bit energy and cell area are not yet competitive with mature e-SRAM, the aggregate bandwidth and in-situ compute density are unmatched for data-intensive and parallelizable workloads.

Roadmaps for pSRAM include:

• Transition from proof-of-concept latches (thermo-optics) to ps-scale, low-energy carrier-depletion or Pockels-effect modulators (Ashtiani, 2024).
• Large-scale integration using hierarchical MZI crossbars, WDM, and on-chip optical comb sources.
• Co-packaged photonic scratchpad or cache memories with optical processors.
• Continued scaling of array size, WDM channel count, and interface electronics to approach the >10 PetaOps regime predicted for hyperspectral, in-memory tensor algebra (Wijeratne et al., 23 Mar 2025, Arockiaraj et al., 31 Jan 2026).

pSRAM arrays thus represent a near-term approach for bridging the gap between optics and digital logic, enabling ultra-high-throughput in-memory computing and overcoming critical electronic memory bottlenecks in data-intensive computing architectures.