Photonic SRAM & Logic Latch Circuits

• Photonic SRAM and logic latch circuits are optical memory elements that use micro-ring resonators and nonlinear interferometric cavities to achieve bistable, addressable states.
• They implement write, hold, and read operations via cross-coupled resonators and optoelectronic feedback, supporting rapid, non-destructive data access.
• Recent designs integrate these devices for in-memory computing with high speeds (up to 40 GHz) and low energy per bit, paving the way for scalable optical processors.

Photonic SRAM (static random access memory) and logic latch circuits are non-volatile or volatile storage and state-holding elements built with photonic device technologies—typically exploiting micro-ring resonators (MRRs), photodiodes (PDs), and nonlinear interferometric cavities, in contrast to purely electronic devices. These memory and logic structures form the foundation for all-optical information storage, state machines, and in-memory computing, directly supporting high-speed, low-latency photonic processors and communication systems. Their architectures leverage interaction between optical (and often electro-optic and optoelectronic) components to achieve bistable, logic, and addressable memory behavior in integrated photonic circuits.

1. Fundamental Architectures: Cross-Coupled Resonators and Nonlinear Latch Topologies

The canonical photonic SRAM bitcell is based on one of two main approaches: cross-coupled micro-ring resonators (MRRs) with optoelectronic feedback, or nonlinear interferometric cavities with intracavity or coupled-cavity bistability (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025, Mabuchi, 2011).

In the MRR-based approach, the cell typically contains two identical silicon micro-ring modulators, each coupled to a waveguide network via directional couplers (e.g., 50:50 splitters). The through-port of each ring is monitored via an integrated photodiode, which applies electrical bias (often via a p-n phase shifter) to the complementary MRR. This cross-coupling creates a regenerative feedback loop: when one ring is ON-resonance, the other is held OFF-resonance. This arrangement yields bistability, with two static logic states corresponding to optical or optically-assisted electrical outputs at the drop-ports (Q, Q*) of the two rings (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025).

Abstractly, these photonic latches are direct analogs of cross-coupled CMOS inverters in standard SRAM; here, however, the “gain” and bistability arise from the photonic device nonlinear response and optoelectronic feedback rather than transistor characteristics.

An alternative paradigm utilizes the intrinsic nonlinear response of optical cavities, especially those exploiting either Kerr ($\chi^{(3)}$) (Mabuchi, 2011) or second-order ($\chi^{(2)}$) (Trivedi et al., 2015) nonlinearities. Two such cavities are cross-coupled in feedback, with external “SET” and “RESET” optical pulses modulating the preferred attractor. Bistability and data retention in these designs result from the S-shaped input-output transfer function of the nonlinear cavity and carefully engineered feedback/interference paths.

2. Device Physics, Bistability Mechanisms, and Key Equations

Discrete-state holding in photonic SRAM and latch circuits arises from optical bistability—realized via sharp resonance tuning of micro-ring resonators or nonlinear cavity S-curves:

• Resonance condition: For an MRR of radius $R$ and effective index $n_\mathrm{eff}$,

$m \lambda_r = 2\pi R n_\mathrm{eff}$

where $m$ is an integer mode number, $\lambda_r$ is the resonant wavelength (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025).

• Quality factor and photon lifetime:

$$Q = \omega_r \tau_{\mathrm{ph}} = \omega_r \frac{\lambda_r Q}{2\pi c}, \quad \tau_{\mathrm{ph}} = \frac{\lambda_r Q}{2\pi c}$$

where $\omega_r = 2\pi c/\lambda_r$ (Kudalippalliyalil et al., 2021).

• Coupling matrix at bus-ring junctions:

$$\begin{pmatrix} E_{\mathrm{thru}} \ E_{\mathrm{drop}} \end{pmatrix} = \begin{pmatrix} t & j \kappa \ j\kappa^* & -t^* \end{pmatrix} \begin{pmatrix} E_{\mathrm{in}} \ 0 \end{pmatrix}$$

with $\chi^{(2)}$0 (Kaiser et al., 25 Mar 2025).

• Photodiode current: $\chi^{(2)}$1 with responsivity $\chi^{(2)}$2 (Kaiser et al., 25 Mar 2025).

In Kerr or second-order nonlinear cavity-based latches, input-output characteristics are modeled via semiclassical or quantum Langevin/Wigner equations. Thresholding and bistability depend on parameters such as $\chi^{(2)}$3-factor, $\chi^{(2)}$4 or $\chi^{(2)}$5 nonlinearity, and phase-matching in multimodal cavities (Mabuchi, 2011, Trivedi et al., 2015).

3. Read/Write/Hold Operations and Memory Array Organization

Photonic SRAM bitcells implement three canonical functions—write, hold, and read:

• Write (“1” / “0”): Write pulses at dedicated wavelengths (e.g., $\chi^{(2)}$6) are injected into the selected cell by reconfiguring access MRRs and/or photodiode gating. For example, a short $\chi^{(2)}$7 pulse biases the cross-coupled photodiode, shifting the resonance of an MRR to $\chi^{(2)}$8, toggling the stored state (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025).
• Hold: In “memory” mode, with no access laser, the cell state is maintained solely by internal feedback: the ON-side photodiode remains forward-biased by residual light, preserving the cross-coupled loop state. No refresh is required.
• Read: Read-enable lasers activate output routing, coupling the bitcell’s Q/Q* (drop-ports) to dedicated waveguides, which direct the stored state to photodetectors or further optical logic. Non-destructive reads are achieved by temporarily activating access MRRs while preserving feedback integrity (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025).

SRAM arrays are constructed in 2D orthogonal wordline/bitline configurations, leveraging waveguide multiplexing or WDM for addressing and high-density integration. Each cell’s area is typically dominated by the MRR footprint and waveguide routing; sharing of common buses and splitters is central to scalability (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025, Kaiser et al., 28 Jun 2025).

4. Quantitative Performance Metrics

Performance is assessed by switching/holding energy, speed (access time and bandwidth), integration density, and noise margins. Notable reported metrics include:

Parameter	O-SRAM (Kudalippalliyalil et al., 2021)	pSRAM (Kaiser et al., 25 Mar 2025)	X-pSRAM (Kaiser et al., 28 Jun 2025)
Max Speed	20 Gb/s	40 GHz	≥10 GHz XOR/read/write
Static Energy/bit	~16.7 aJ	0.03 pJ	8.8 fJ (write), 2.2 fJ (read), 13.2 fJ (XOR)
Dynamic Energy	1.04 pJ/bit	0.6 pJ/bit	–
Bitcell Area	2400 µm²	95,700 µm²	≈0.1 mm²
Optical BW	36 GHz (Q=6500)	~40 GHz (Q=1e4–5)	10 GHz/channel (WDM)

Photon lifetime and MRR modulation bandwidth ($\chi^{(2)}$9) set access rates, while power consumption (optical bias, switching laser energy) and hold static noise margin (HSNM, as extracted from butterfly curves) determine robustness. Achievable energy-delay products ($R$0 J·s in O-SRAM) position photonic SRAM as competitive with (and in bandwidth, surpassing) advanced electronic SRAM (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025, Kaiser et al., 28 Jun 2025).

5. Embedded Photonic Logic Latches and In-Memory Computing

Beyond elemental storage, photonic SRAM latches serve as primitives for universal sequential and combinational logic. Cross-coupled MRR/PD structures can be extended to implement SR, D, and master-slave latches via the addition of input selection rings, clock gating, and cascaded waveguide routing (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025, Ashtiani, 2024, Mabuchi, 2011).

Recent architectures, such as X-pSRAM, embed dedicated compute rings within the SRAM cell to realize in-place Boolean operations—most notably optical XOR—enabling in-memory computing at ≥10 GHz and <14 fJ/bit by leveraging WDM for simultaneous multi-bit logic (Kaiser et al., 28 Jun 2025). The functional mapping is achieved by exploiting the resonance and through-port/drop-port interference of additional MRRs, with MMI-based combiners (Kaiser et al., 28 Jun 2025).

Nonlinear cavity-based networks also demonstrate minimal optical SR-latches, AND, and NAND functionality through coupled $R$1 cavities with external phase-shift and amplitude control; fan-out and gain are achieved by hierarchical interferometric and cavity design (Trivedi et al., 2015, Mabuchi, 2011).

6. Integration, Fabrication, and Scalability

All principal device types—MRRs, p-n phase shifters, Ge photodiodes, MMIs—are available in contemporary silicon photonics foundries (SOI, GF45SPCLO), supporting multi-hundred Gbps aggregate memory bandwidth (Kudalippalliyalil et al., 2021, Kaiser et al., 25 Mar 2025, Kaiser et al., 28 Jun 2025). Tiling is typically orthogonal (row/column), with passive splitters for waveguide power distribution and WDM for enhanced addressing capability.

Thermo-optic or carrier-injection tuning is required for post-fabrication resonance correction; variation $R$2 pm and PD responsivity variation ±10% are typical (Kaiser et al., 28 Jun 2025). Co-design of bus, coupling gaps, and ring radii allows footprint scaling to sub-100 µm² per cell. Independent supply lasers or bias optical power ensure per-cell logic swing and isolate adjacent cells—key for array scalability (Ashtiani, 2024).

Limitations remain in comparison to scaled electronic SRAM: increased footprint ($R$310× at present), the requirement for continuous supply light (volatility), and tight fabrication tolerances. Nonetheless, these photonic solutions eliminate electrical interconnect delay, bitline capacitance, and enable bandwidth scaling via frequency and spatial multiplexing.

7. Comparison of Nonlinearity Mechanisms and Outlook

Second-order ($R$4) nonlinear cavities provide higher energy efficiency at moderate $R$5 ($R$6) versus third-order ($R$7, e.g., Kerr) devices, which only approach comparable energy at $R$8 (Trivedi et al., 2015). For instance, at $R$9, $n_\mathrm{eff}$0 gates achieve $n_\mathrm{eff}$1W and SNR $n_\mathrm{eff}$2 dB, versus $n_\mathrm{eff}$3W for $n_\mathrm{eff}$4. Switching times are set by cavity photon lifetime and are typically in the 10–50 ps range (Trivedi et al., 2015, Mabuchi, 2011).

Recent developments in programmable photonic meshes demonstrate that universal optical logic gates (composed of cascaded MRRs, MZIs, and PDs) can be interconnected to realize SR-latches on chip, with memory fabric scaling supported by per-cell optical supply and WDM addressing (Ashtiani, 2024).

Overall, photonic SRAM and logic latch circuits provide a manufacturable path to ultra-fast, energy-efficient, and scalable on-chip memory and in-situ logic, with direct integration into photonic networks and processors. These architectures extend the von Neumann bottleneck by fusing photonic memory and logic at the device level, enabling novel computational and networking topologies for next-generation integrated photonic systems.