Phase-Cycling Algorithm in AQFP Design

• Phase-cycling algorithm is an integer-linear programming based clock scheduling method that optimally balances AQFP circuits by combining phase-skipping and phase-alignment.
• It reduces excessive buffer overhead by globally assigning clock levels, transforming local buffer repair into a comprehensive delay management strategy.
• The formulation integrates throughput constraints to trade off between area savings and performance, leading to significant improvements over conventional methods.

In Adiabatic Quantum-Flux-Parametron (AQFP) digital design, the phase-cycling algorithm denotes an integer-linear-programming-based clock phase scheduling method that jointly exploits phase-skipping and phase-alignment to reduce path-balancing overhead while optionally enforcing a throughput target. The method was introduced for AQFP circuits, where every logic gate and splitter must be clocked and where data transfer is constrained by overlapping clock phases and strict setup/hold conditions. In conventional balanced clocking, structural imbalance between connected gates is repaired by inserting clocked buffers; because AQFP buffers and splitters are themselves active, clocked cells, this overhead can dominate the implementation, with buffers consuming up to 90% of total area in some designs. The phase-cycling formulation recasts this as a global scheduling problem over gate levels, cycle skips, and residual phase skips, rather than a purely local buffer-repair problem (Aviles et al., 4 Oct 2025).

1. AQFP clocking context and the path-balancing problem

AQFP logic is a superconducting digital technology characterized in the source work as offering orders of magnitude lower power consumption than CMOS. Its scalability, however, is challenged by excessive buffer overhead arising from path-balancing constraints. The central timing constraint is that adjacent stages can exchange data only when their clock phases overlap in a way that satisfies setup and hold requirements. Under conventional balanced clocking, every logic level advances one phase at a time, so any level mismatch between two connected elements must be compensated by inserting additional clocked buffers (Aviles et al., 4 Oct 2025).

This design regime makes clock assignment unusually consequential. Unlike in logic families where a buffer is comparatively passive, AQFP buffers and splitters are active clocked cells. A plausible implication is that level assignment, clock overlap, and structural balancing are not separable concerns: they determine both functional legality and much of the final area. The phase-cycling algorithm addresses this by assigning clock levels globally over the AQFP directed acyclic graph (DAG), so that imbalances are absorbed by the clocking structure whenever possible rather than by inserted buffers (Aviles et al., 4 Oct 2025).

2. Combination of phase-skipping and phase-alignment

The algorithm unifies two previously separate AQFP design techniques. Phase-skipping is a circuit-level relaxation in which the clock has more overlapping phases, allowing data transfer between gates clocked with non-consecutive phases. If the clock has $N$ phases and the phase-skipping span is $P$, then for an edge $(i,j)$ with level imbalance $\Delta L_{ij}$, phase-skipping alone yields the buffer cost

$$\left\lfloor \frac{(\Delta L_{ij}-1)}{P} \right\rfloor .$$

Phase-alignment is instead an architectural technique that repeats input patterns across multiple clock cycles using NDRO-based input repetition. It absorbs imbalances that are exact multiples of a full clock cycle with zero buffer cost. For this reason, the source paper refers to it as a cycle-skip: it does not skip overlapping phases within one cycle, but allows a connection to span whole clock cycles (Aviles et al., 4 Oct 2025).

The combined method first lets phase-alignment absorb whole-cycle multiples and then uses phase-skipping on the residual within-cycle imbalance. The residual buffer cost is given as

$$\left\lfloor \frac{(\Delta L_{ij} - 1) \bmod N}{P} \right\rfloor .$$

This creates a non-monotonic, aperiodic cost landscape, because small changes in imbalance can change how much is handled by cycle-skipping versus phase-skipping, which in turn changes the number of inserted buffers. The complementarity between the two mechanisms is the main source of the reported gains: phase-alignment is best for large imbalances that are exact multiples of the clock cycle, whereas phase-skipping is best for smaller residual imbalances inside a cycle. The paper gives a representative example in which an 11-level imbalance can be resolved with only one buffer under the combined scheme, compared with 11 buffers under traditional balancing (Aviles et al., 4 Oct 2025).

3. Integer-linear programming formulation

The phase-cycling method models the AQFP circuit as a directed acyclic graph $G=(V,E)$, with one node per logic element and one edge per connection. The core decision variables are integer clock levels $L_i$ assigned to nodes and per-edge variables describing buffer insertion and skip structure. The optimization objective is

$\text{Minimize:} \sum_{E_{ij}=1} C_{ij},$

where $C_{ij}$ is the number of buffers inserted on edge $P$0 (Aviles et al., 4 Oct 2025).

To handle the irregular cost surface induced by the combined use of phase-skipping and phase-alignment, the formulation decomposes the buffer cost into two independent integer variables. The variable $P$1 models phase-skipping buffers, while $P$2 models cycle-skipping buffers. The number of full-cycle skips on edge $P$3 is denoted $P$4. The paper gives the following per-edge constraints:

$P$5

$P$6

$P$7

$P$8

with all variables integral:

$P$9

These constraints enforce consistency between level differences, residual phase skips, and full-cycle skips. The $(i,j)$0 constraint prevents arbitrary long-range cycle skipping; the source work states that this matters for physical place-and-route because excessive level differences can cause wirelength or timing issues. The formulation also constrains primary inputs to levels 3 through 5, matching the phase-alignment convention with repeated inputs, and forces all primary outputs to share a common level. The resulting schedule is intended to be legal for subsequent AQFP place-and-route (Aviles et al., 4 Oct 2025).

4. Throughput-aware extension and area–performance trade-offs

Phase-alignment reduces buffer count by repeating inputs, but this repetition lowers throughput. The paper therefore extends the ILP to incorporate throughput constraints explicitly. Its key observation is that throughput is not determined solely by the maximum skip on a single edge; rather, it depends on the cumulative number of cycle-skips along a path. To represent this, the formulation introduces a node variable $(i,j)$1, interpreted as the number of input repetitions required to align data at node $(i,j)$2 (Aviles et al., 4 Oct 2025).

The additional constraints are

$(i,j)$3

$(i,j)$4

The first propagates accumulated cycle-skipping along paths, and the second imposes a user-specified repetition bound. The throughput reduction is then expressed as

$(i,j)$5

because each input must be presented for $(i,j)$6 cycles. This makes the area/performance trade-off explicit: larger $(i,j)$7 permits more cycle-skipping and thus fewer buffers, but lowers throughput; smaller $(i,j)$8 preserves throughput at the cost of additional buffering. This suggests that the algorithm is not merely a minimum-area scheduler, but a constrained multi-objective optimizer in which structural timing relaxation is parameterized directly by acceptable input repetition (Aviles et al., 4 Oct 2025).

5. Reported results and benchmark behavior

The evaluation reported in the source work uses standard AQFP benchmarks and a 10-minute ILP solve cap per circuit. Two baselines are used: state-of-the-art 1-phase-skipping and state-of-the-art phase-alignment. For the area-only formulation, the combined method is reported to achieve an average 25.7% area reduction relative to phase-skipping alone and 11.6% relative to phase-alignment alone; the abstract summarizes these as 25% and 11%. The benchmark table reports both buffer/splitter counts and maximum phase skip, and the proposed method is described as consistently lowering total BS/JJ cost across many benchmarks (Aviles et al., 4 Oct 2025).

For the throughput-aware formulation, the comparison against phase-alignment uses the latter’s reported maximum phase skip and converts that value to throughput via

$(i,j)$9

for a 4-phase setup. Under the throughput constraint, the proposed approach achieves an average 6.8% area savings while increasing throughput by 2.62$\Delta L_{ij}$0 over the phase-aligned baseline (Aviles et al., 4 Oct 2025).

Formulation	Baseline	Reported average outcome
Area-only	Phase-skipping alone	25.7% area reduction
Area-only	Phase-alignment alone	11.6% area reduction
Throughput-constrained	Phase-aligned method	6.8% area savings and 2.62$\Delta L_{ij}$1 increased throughput

The significance of these results lies in the joint scheduling of whole-cycle and within-cycle relaxations. Rather than treating throughput degradation as an unavoidable side effect of alignment, the ILP exposes it as a controlled design parameter. The reported averages therefore support the claim that the unified formulation outperforms either constituent technique used in isolation (Aviles et al., 4 Oct 2025).

6. Scope of the term and common misconceptions

A common misconception is to treat phase cycling as a field-independent algorithm with a single established meaning. The AQFP phase-cycling algorithm is a clock phase scheduling method for superconducting digital circuits, but the same term is also used in several unrelated technical literatures. In single-quantum satellite-transition magic angle spinning, phase cycling refers to pulse-phase selection over a five-pulse sequence using coherence-order selection rules such as $\Delta L_{ij}$2 and receiver-phase correction $\Delta L_{ij}$3 (Malavé, 2014). In phase-regularized MRI reconstruction, phase cycling denotes random shifting of phase wraps during iterative optimization to avoid repeated regularization artifacts near $\Delta L_{ij}$4 discontinuities (Ong et al., 2017). In non-collinear optical 2D coherent spectroscopy, it denotes controlled $\Delta L_{ij}$5 and $\Delta L_{ij}$6 phase toggling of excitation pulses and algebraic combinations such as $\Delta L_{ij}$7 to isolate the third-order four-wave-mixing signal (Munoz et al., 2020). In population-detected optical multidimensional spectroscopy, it can mean either nested phase stepping or simultaneous “cogwheel” phase updates defined by winding numbers (Jayachandran et al., 2024).

The AQFP usage is therefore domain-specific. Its essential objects are not pulse phases, coherence pathways, or wrapped image phases, but integer clock levels, cycle skips, and residual phase skips on a circuit DAG. The lexical overlap with spectroscopy and imaging terminology should not obscure that distinction. Within AQFP design, the phrase names a global scheduling algorithm that generalizes clock assignment from local buffer repair to constrained optimization over phase levels, whole-cycle repetitions, and throughput (Aviles et al., 4 Oct 2025).